Intel 82555 manual Management Data Interface, MDI Frame Structure

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Networking Silicon — 82555

7.0Management Data Interface

The 82555 provides status and accepts management information through the Management Data Interface (MDI). This is accomplished through read and write operations to various registers in accordance with the IEEE 802.3u MII specification.

7.1MDI Frame Structure

Data read from or written to a particular register is called a management frame and is sent serially over the MDIO pin synchronously to the MDC signal. Read and write cycles are viewed from the perspective of the controller. Thus, the controller always drives the start, opcode, PHY address, and register address onto the MDIO pin. For read cycles, the controller drives the transition bits and data onto the MDIO pin; for write cycles, to the 82555. The controller drives addresses and data on the falling edge of the MDC signal, and the 82555 latches the data on the rising edge of the MDC signal. The following list defines protocol terms:

PREAMBLE At the beginning of each transaction, the controller send a sequence of 32 contiguous logic one bits on the MDIO pin with corresponding cycles on the MDC pin for synchronization by the 82555.

ST

This field contains the value of 01b indicating the start of a frame.

OP

This is a 2-bit field containing one of the following two operation codes: 10b (read)

 

or 01b (write).

PHYAD

This field is a 5-bit address of the 82555 device that provides support for 32 unique

 

PHY addresses. The controller drives the value written into the PHYAD portion of

 

the MDI register in this field.

REGAD

This field is a 5-bit address of a specific register within the 82555. This provides

 

support for 32 unique registers. The desired register address is specified by the

 

value written to the MDI register.

TA

This field contains a 2-bit value specifying the period during a read cycle that no

 

device may actively drive the MDIO signal. During a read transaction, the 82555

 

should not drive the MDIO signal in the first bit time; however, it will drive a 0b in

 

the second bit time. During a write transaction, the controller drives the pattern of

 

10b to fill this time.

DATA

This field contains 16 bits of data driven by the 82555 on a read transaction or by

 

the controller on a write transactions. This data is either control or status parameters

 

passed between the controller and the 82555.

IDLE

During the idle state, the MDIO signal is in a high impedance state. The MDIO

 

driver is disabled, and the 82555 will pull the MDIO signal high to a logic 1.

Datasheet

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Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Functional Overview IntroductionCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Repeater mode only Transmit Error From RICYes Pin Numbers and Labels Pin DefinitionsPin Types Clock PinsTwisted Pair Ethernet TPE Pins Media Independent Interface MII PinsMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins VCC Power and Ground PinsVSS 100BASE-TX Transmit Blocks 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Clock GenerationInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding DiagramTransmit Driver 100BASE-TX Receive BlocksVendor Model/Type 100BASE-TX Collision Detection Auto-Negotiation 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Link IntegrityAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Receive Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Transmit Blocks10BASE-T Jabber Control Function 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Link Integrity10BASE-T Full Duplex Networking Silicon Datasheet Special Repeater Features Repeater ModeConnectivity Clock Signal Example MDI Frame Structure Management Data InterfaceTransition Bits Name Description DefaultMDI Registers MDI Registers 010BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsPriority Technology Bit Setting TechnologyAuto-Negotiation Functionality DescriptionPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Scrambler Bypass Reset and Miscellaneous Test ModesReset LoopbackNumber Code Test Instruction Select Input to Tout Test Instruction CodingGeneral Operating Conditions Electrical Specifications and Timing ParametersDC Characteristics Absolute Maximum RatingsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsMII Clock Specifications AC CharacteristicsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0
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