Intel 82555 manual 100BASE-TX Receive Blocks, Transmit Driver, Vendor Model/Type

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82555 — Networking Silicon

4.2.4Transmit Driver

The transmit differential lines are implemented with a digital slope controlled current driver that meets the TP-PMD specifications. Current is sunk from the isolation transformer by the transmit differential pins. The conceptual transmit differential waveform for 100 Mbps is illustrated in the following figure.

(V TDP -VTDN )
+1V
0V	t
-1V
ITDP
40mA
20mA
0	t
ITDN
40mA
20mA
0	t

Figure 7. Conceptual Transmit Differential Waveform

The magnetics module that is external to the 82555 converts ITDP and ITDN to 2.0 Vpp, as required by the TP-PMD specification. The same magnetics used for 100BASE-TX mode should also work

in 10BASE-T mode. The following is a list of current magnetics modules available from several vendors:

Table 3. Magnetics Modules

Vendor	Model/Type	100BASE-TX	10BASE-T


Delta	LF8200A	Yes	Yes

Pulse Engineering	PE-68515	Yes	Yes

Pulse Engineering	H1012	Yes	Yes

4.3100BASE-TX Receive Blocks

The receive subsection of the 82555 accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the 82555 will accurately receive valid data from Category 5 (CAT5) UTP and Type 1 STP cable of length well in excess of 100 meters.

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Datasheet

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Contents Product Features 82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon Revision DescriptionContents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon 100 Mbps Mode Architectural Overview10 Mbps Mode MII TX InterfaceMedia Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Definitions Pin Numbers and LabelsClock Pins Twisted Pair Ethernet TPE PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins LED Pins External Bias PinsMiscellaneous Control Pins VSS Power and Ground PinsVCC 100BASE-TX Adapter Mode Operation Symbol 5B Symbol Code 4B Nibble Code100BASE-TX Transmit Clock Generation 100BASE-TX Transmit Blocks2 100BASE-TX Scrambler and MLT-3 Encoder InvalidNRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit FramingVendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection 100BASE-TX Link Integrity and Auto-Negotiation Solution Combination Tx/T4 Auto-Negotiation SolutionLink Integrity Auto-NegotiationAdapter Mode Addresses Auto 10/100 Mbps Speed SelectionNetworking Silicon Datasheet 10BASE-T Functionality in Adapter Mode 10BASE-T Transmit Clock Generation10BASE-T Transmit Blocks 10BASE-T Receive Blocks3 10BASE-T Error Detection and Reporting 10BASE-T Collision Detection10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example Management Data Interface MDI Frame StructureBits Name Description Default MDI RegistersMDI Registers 0 TransitionRegister 1 Status Register Bit Definitions 10BASE-TRegister 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16Register 17 82555 Special Control Bit Definitions 100BASE-TX150 Register 22 Receive Symbol Error Counter Bit Definitions Actled LiledBit Setting Technology Auto-Negotiation FunctionalityDescription Priority TechnologyParallel Detect and Auto-Negotiation PriorityAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset and Miscellaneous Test Modes ResetLoopback Scrambler BypassTest Instruction Coding Number Code Test Instruction Select Input to ToutElectrical Specifications and Timing Parameters DC CharacteristicsAbsolute Maximum Ratings General Operating Conditions11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pinsSymbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Timing Parameters MII Clocks AC TimingRepeater Mode Timing Parameters RXC tri-stated aTransmit Packet Timing Parameters Squelch Test Timing ParametersJabber Timing Parameters Receive Packet Timing Parameters11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing ParametersReset Timing Parameters 11.4.11 X1 Clock Specifications11.4.12 100BASE-TX Transmitter AC Specification X1 Clock SpecificationsSymbol Description Min Norm Max 12.0 82555 Package Information10.0