Intel 82555 manual 100BASE-TX Adapter Mode Operation, 100BASE-TX Transmit Clock Generation

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Networking Silicon — 82555

4.0100BASE-TX Adapter Mode Operation

4.1100BASE-TX Transmit Clock Generation

A 25 MHz crystal or a 25 MHz oscillator is used to drive the 82555’s X1 and X2 pins. The 82555 derives its internal transmit digital clocks from this crystal or oscillator input. The Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± 0.0005% (50 PPM).

4.2100BASE-TX Transmit Blocks

The transmit subsection of the 82555 accepts nibble-wide data on the TXD[3:0] lines when TXEN is asserted (high). The transmit subsection passes data unconditionally to the 4B/5B encoder as long as TXEN is active.

The 4B/5B encoder accepts nibble-wide data (4 bits) from the MAC and compiles it into 5-bit-wide parallel symbols. These symbols are scrambled and serialized into a 125 Mbps bit stream, converted by the analog transmit driver into a MLT-3 waveform format, and transmitted onto the Unshielded Twisted Pair (UTP) or Shielded Twisted Pair (STP) wire.

4.2.1100BASE-TX 4B/5B Encoder

The 4B/5B encoder complies with the IEEE 802.3u 100BASE-TX standard. Four bits are encoded according to the transmit 4B/5B lookup table. The lookup table matches a 5-bit code to each 4-bit code.

The table below illustrates the 4B/5B encoding scheme associated with the given symbol.

Table 2. 4B/5B Encoder

Symbol	5B Symbol Code	4B Nibble Code


0	11110	0000

1	01001	0001

2	10100	0010

3	10101	0011

4	01010	0100

5	01011	0101

6	01110	0110

7	01111	0111

8	10010	1000

9	10011	1001

A	10110	1010

B	10111	1011

C	11010	1100

D	11011	1101

Datasheet

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Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Numbers and Labels Pin DefinitionsTwisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins VSS Power and Ground PinsVCC Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit BlocksInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding DiagramVendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-NegotiationAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example MDI Frame Structure Management Data InterfaceMDI Registers Bits Name Description DefaultMDI Registers 0 Transition10BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsAuto-Negotiation Functionality Bit Setting TechnologyDescription Priority TechnologyPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler BypassNumber Code Test Instruction Select Input to Tout Test Instruction CodingDC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating ConditionsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsSymbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0