Intel 82555 manual 10BASE-T Functionality in Adapter Mode, 10BASE-T Transmit Clock Generation

Page 25

Networking Silicon — 82555

5.010BASE-T Functionality in Adapter Mode

5.110BASE-T Transmit Clock Generation

The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The 82555 provides the transmit clock and receive clock to the MAC at 2.5 MHz.

5.210BASE-T Transmit Blocks

5.2.110BASE-T Manchester Encoder

After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs the Manchester encoding. The Manchester code always has a mid-bit transition. If the value is 1b then the transition is from low to high. If the value is 0b then the transition is from high to low. The boundary transition occurs only when the data changes from bit to bit. For example, if the value is 10b, then the change is from high to low; if 01b, then the change is from low to high.

5.2.210BASE-T Driver and Filter

Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented inside the chip. This allows the two technologies to share the same magnetics. The 82555 supports both technologies through one pair of transmit differential pins and by externally sharing the same magnetics.

In 10 Mbps mode, the 82555 begins transmitting the serial Manchester bit stream within 3 bit times (300 nanoseconds) after the MAC asserts TXEN. In 10 Mbps mode the line drivers use a pre- distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second half of “wide” (100 ns) Manchester pulses and maintain a full drive level during all narrow (50 ns) pulses and the first half of the wide pulses. This reduces line overcharging during wide pulses, a major source of jitter.

5.310BASE-T Receive Blocks

5.3.110BASE-T Manchester Decoder

The 82555 performs Manchester decoding and timing recovery when in 10 Mbps mode. The Manchester encoded data stream is decoded from the receive differential pair to separate Receive Clock and Receive Data lines from the differential signal. This data is transferred to the controller at 2.5 MHz/nibble through the MII. The high-performance circuitry of the 82555 exceeds the IEEE

802.3 jitter requirements.

5.3.210BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter

In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The filter is implemented inside the 82555 for supporting single magnetics that are shared with the 100BASE-TX side. The input differential voltage range for the

Datasheet

21

Page 24 Page 26
Image 25
Page 24 Page 26
Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Functional Overview IntroductionCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Repeater mode only Transmit Error From RICYes Pin Numbers and Labels Pin DefinitionsTwisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins VCC Power and Ground PinsVSS Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit BlocksInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding DiagramTransmit Driver 100BASE-TX Receive BlocksVendor Model/Type 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-NegotiationAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Special Repeater Features Repeater ModeConnectivity Clock Signal Example MDI Frame Structure Management Data InterfaceMDI Registers Bits Name Description DefaultMDI Registers 0 Transition10BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsAuto-Negotiation Functionality Bit Setting TechnologyDescription Priority TechnologyPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler BypassNumber Code Test Instruction Select Input to Tout Test Instruction CodingDC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating ConditionsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsMII Clock Specifications AC CharacteristicsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0
Top Page Image Contents