Intel 82555 manual Reset and Miscellaneous Test Modes, Loopback, Scrambler Bypass, Test Port

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Networking Silicon — 82555

10.0Reset and Miscellaneous Test Modes

10.1Reset

When the 82555 RESET signal is asserted (high), all internal circuits are reset. TXC and RXC should run continuously even though RESET is active. The 82555 may also be reset through the MDI reset bit.

10.2Loopback

When the loopback pin is being driven high, the 82555 executes a loopback diagnostics operation. This mode can also be accessed through the MDI registers.

10.3Scrambler Bypass

When the Scrambler Bypass pin is active, the 82555 bypasses the scrambler/descrambler. This mode can also be accessed through the MDI registers.

10.4Test Port

When the TESTEN pin is high, the test pins provide a test access port for the 82555. In test mode, the 82555 will default to address 1. The 82555 has a simple Test Access Port (TAP) from which all the test modes are selected and test instructions are operated. The TAP is controlled by a simple mechanism and handshake. Activation of all test modes requires simple hardware. The TAP signals connected to the 82555 blocks and periphery control the 82555’s mode of operation to allow simple testing and internal built-in self testing.

The test instruction are shifted into the Test Instruction Shift Register (TISR) through the TIN pin. The TIN pin is sampled on the rising edge of the TCK input signal. The instruction is transferred from the TISR to the Test Instruction Register (TIR) when TESTEN is sampled high on the rising edge of TCK. As a general rule, all the TAP input and output pins are activated by the rising edge of TCK. If TCK is a constant clock signal, then TESTEN must be 1 clock pulse width.

When the TIR receives a new instruction, the instruction is decoded into control signals and synchronized to the 10 MHz clock. These control signals set the 82555 blocks into various test modes. In order to achieve stable synchronization between the clock signal (X1) and the TCK signal, the TCK input signal frequency should be less than or equal to half of the clock input signal frequency.

Datasheet

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Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Numbers and Labels Pin DefinitionsTwisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins Power and Ground Pins VCCVSS Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit BlocksInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding Diagram100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-NegotiationAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example MDI Frame Structure Management Data InterfaceMDI Registers Bits Name Description DefaultMDI Registers 0 Transition10BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsAuto-Negotiation Functionality Bit Setting TechnologyDescription Priority TechnologyPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler BypassNumber Code Test Instruction Select Input to Tout Test Instruction CodingDC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating ConditionsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsAC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0