Intel 82555 manual Register 1 Status Register Bit Definitions, 10BASE-T

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Networking Silicon — 82555

Bit(s)	Name		Description	Default	R/W


11	Power-Down	This bit sets the 82555 into a low power mode.		0	RW
		1	= Power-down enabled
		0	= Power-down disabled (normal operation)

10	Isolate	This bit allows the 82555 to electrically isolate the Media		0	RW
		Independent Interface. When the MII is isolated, the
		82555 does not respond to TXD[3:0], TXEN, and TXERR
		input signals. Also, the 82555 presents high impedance
		on its TXC, RXC, RXDV, RXERR, RXD[3:0], COL, and
		CRS output signals. In the TX mode, the 82555 responds
		to management transactions.
		1	= Electrically isolate MII
		0	= Normal operation

9	Restart Auto-	This bit restarts the Auto-Negotiation process and is self-		0	RW
	Negotiation	clearing.			SC
					SC
		1	= Restart Auto-Negotiation process
		0	= Normal operation

8	Duplex Mode	This bit controls the duplex mode when Auto-Negotiation		0	RW
		is disabled. If the 82555 reports that it is only able to
		operate in one duplex mode, the value of this bit shall
		correspond to the mode which the 82555 can operate.
		When the 82555 is placed in Loopback mode, the
		behavior of the PHY shall not be affected by the status of
		this bit, bit 8.
		1	= Full Duplex
		0	= Half Duplex

7	Collision Test	This bit will force a collision in response to the assertion		0	RW
		of the transmit enable signal.
		1	= Force COL
		0	= Do not force COL

6:0	Reserved	These bits are reserved and should be set to 0000000b.		0	RW

7.2.1.2Register 1: Status Register Bit Definitions

Bit(s)	Name		Description	Default	R/W


15	100BASE-T4	1 = 82555 able to perform 100BASE-T4		--	RO
		0	= 82555 not able to perform 100BASE-T4		P

14	100BASE-TX Full	1	= 82555 able to perform full duplex 100BASE-TX	--	RO
	Duplex	0	= 82555 not able to perform full duplex in repeater		P
		0	= 82555 not able to perform full duplex in repeater		P
		mode

13	100 Mbps Half	1	= 82555 able to perform half duplex 100BASE-TX	--	RO
	Duplex	0	= 82555 not able to perform 100BASE-TX		P
		0	= 82555 not able to perform 100BASE-TX		P

12	10 Mbps Full	1	= 82555 able to operate at 10 Mbps in full duplex	--	RO
	Duplex	mode			P
					P
		0	= 82555 not able to operate in full duplex mode in
		10BASE-T

11	10 Mbps Half	1	= 82555 able to operate at 10 Mbps in half duplex	--	RO
	Duplex	mode			P
					P
		0	= 82555 not able to operate in 10BASE-T

10:7	Reserved	These bits are reserved and should be set to 0000b.		0	RO

Datasheet

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Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Numbers and Labels Pin DefinitionsTwisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin TypesMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins Power and Ground Pins VCCVSS Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit BlocksInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding Diagram100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-NegotiationAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example MDI Frame Structure Management Data InterfaceMDI Registers Bits Name Description DefaultMDI Registers 0 Transition10BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsAuto-Negotiation Functionality Bit Setting TechnologyDescription Priority TechnologyPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler BypassNumber Code Test Instruction Select Input to Tout Test Instruction CodingDC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating ConditionsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsAC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0