Intel 82555 manual 10BASE-T Collision Detection, 10BASE-T Link Integrity

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82555 — Networking Silicon

Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10BASE-T standard.

The following line activity is determined to be inactive and is rejected:

Differential pulses of peak magnitude less than 300 mV.

Continuous sinusoids with a differential amplitude less than 6.2 Vpp and frequency less than 2 MHz.

Sine waves of a single cycle duration starting with 0° or 180° phase that have a differential

amplitude less than 6.2 Vpp and a frequency of at least 2 MHz and not more than 16 MHz. These single-cycle sine waves are discarded only if they are preceded by 4 bit times (400 nanoseconds) of silence.

All other activity is determined to be either data, link test pulses, Auto-Negotiation fast link pulses, or the idle condition. When activity is detected, the carrier sense signal is asserted to the MAC.

5.3.310BASE-T Error Detection and Reporting

In 10 Mbps mode, the 82555 can detect errors in the receive data. The following condition is considered an error:

The receive pair’s voltage level drops to the idle state during reception before the end-of-frame bit is detected (250 nanoseconds without mid-bit transitions).

5.410BASE-T Collision Detection

Collision detection in 10 Mbps mode is indicated by simultaneous transmission and reception. If the 82555 detects this condition, it asserts a collision indication to the controller.

5.510BASE-T Link Integrity

The link integrity in 10 Mbps works with link pulses. The 82555 senses and differentiates those link pulses from fast link pulses and from 100BASE-TX idles. In the first and last case, the 82555 activates parallel detection of the respective technology; and in the second case, Auto-Negotiation. The 10 Mbps link pulses or normal link pulses are driven in the transmit differential pair line but are 100 ns wide and have levels from 0 V to 5 V. The link beat pulse is also used to determine if the receive pair polarity is reversed. If it is, the polarity is corrected internally.

5.610BASE-T Jabber Control Function

The 82555 contains a jabber control function that inhibits transmission after a specified time window when enabled. In 10 Mbps mode, the jabber timer is set to a value between 26.2 ms and 39 ms. If the 82555 detects continuous transmission that is greater than this time period, it prevents further transmissions from onto the wire until it detects that the MAC transmit enable signal has been inactive for at least 314 ms.

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Datasheet

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Contents Product Features 82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon Revision DescriptionContents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon 100 Mbps Mode Architectural Overview10 Mbps Mode MII TX InterfaceMedia Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Definitions Pin Numbers and LabelsMedia Independent Interface MII Pins Clock PinsTwisted Pair Ethernet TPE Pins Pin TypesMedia Access Control/Repeater Interface Control Pins LED Pins External Bias PinsMiscellaneous Control Pins VSS Power and Ground PinsVCC 100BASE-TX Transmit Clock Generation 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Blocks2 100BASE-TX Scrambler and MLT-3 Encoder InvalidNRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit FramingVendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection Link Integrity 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Auto-NegotiationAdapter Mode Addresses Auto 10/100 Mbps Speed SelectionNetworking Silicon Datasheet 10BASE-T Transmit Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Receive Blocks10BASE-T Link Integrity 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Jabber Control Function10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example Management Data Interface MDI Frame StructureMDI Registers 0 Bits Name Description DefaultMDI Registers TransitionRegister 1 Status Register Bit Definitions 10BASE-TRegister 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16Register 17 82555 Special Control Bit Definitions 100BASE-TX150 Register 22 Receive Symbol Error Counter Bit Definitions Actled LiledDescription Bit Setting TechnologyAuto-Negotiation Functionality Priority TechnologyParallel Detect and Auto-Negotiation PriorityAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Loopback Reset and Miscellaneous Test ModesReset Scrambler BypassTest Instruction Coding Number Code Test Instruction Select Input to ToutAbsolute Maximum Ratings Electrical Specifications and Timing ParametersDC Characteristics General Operating Conditions11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pinsSymbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Timing Parameters MII Clocks AC TimingRepeater Mode Timing Parameters RXC tri-stated aTransmit Packet Timing Parameters Squelch Test Timing ParametersJabber Timing Parameters Receive Packet Timing Parameters11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing ParametersReset Timing Parameters 11.4.11 X1 Clock Specifications11.4.12 100BASE-TX Transmitter AC Specification X1 Clock SpecificationsSymbol Description Min Norm Max 12.0 82555 Package Information10.0