Intel 82555 manual Miscellaneous Control Pins

Page 15

Networking Silicon — 82555

3.8Miscellaneous Control Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

RESET

1

I

Reset. The Reset signal is active high and resets the 82555. A reset pulse

 

 

 

width of at least 1 μs should be used.

 

 

 

 

FRC100

51

I

This pin is multiplexed and can be used for one of the following:

(MACTYP)

 

 

Force 100/10 Mbps. In repeater mode, this pin configures the repeater to

 

 

 

either 100 Mbps (active high) or to 10 Mbps (active low).

 

 

 

MAC Type. In DTE (adapter) full duplex mode, if this input signal is high, the

 

 

 

82555 drives 82557 mode. If this input signal is low, the 82555 drives a

 

 

 

generic MII MAC mode.

 

 

 

 

PHYA4

22

I

This pin is multiplexed and can be used for one of the following:

(TIN)

 

 

PHY Address 4. In repeater mode, this signal represents the fifth bit for

 

 

 

address port configuration.

 

 

 

TIN. If the Test Enable signal is active, this signal is used as the Test Input

 

 

 

data.

 

 

 

 

PHYA3

52

I/O

This pin is multiplexed and can be used for one of the following:

(SLVTRI)

 

 

PHY Address 3. In repeater mode, this signal represents the fourth bit for

 

 

 

address port configuration.

 

 

 

Slave Tri-state.In DTE (adapter) mode, this output operates in conjunction

 

 

 

with the T4 Advanced signal. When both are active, the slave PHY is inactive

 

 

 

and tri-states all its outputs.

 

 

 

 

PHYA2

6

I

This pin is multiplexed and can be used for one of the following:

(LISTAT)

 

 

PHY Address 2. In repeater mode, this signal represents the third bit for

 

 

 

address port configuration.

 

 

 

Link Status. In DTE (adapter) mode, if T4 Advance is active, the LISTAT_N

 

 

 

signal is active low and the slave PHY link is valid.

 

 

 

 

PHYA1

25

I

This pin is multiplexed and can be used for one of the following:

(TEXEC)

 

 

PHY Address 1. In repeater mode, this signal represents the second bit for

 

 

 

address port configuration.

 

 

 

Test Execute. If Test Enable is asserted, this signal acts as the test

 

 

 

execution command indicating that the pin 22 is being used as the Test Input

 

 

 

pin.

 

 

 

 

PHYA0

24

I

This pin is multiplexed and can be used for one of the following:

(TCK)

 

 

PHY Address 0. In repeater mode, this signal represents the first bit for

 

 

 

address port configuration.

 

 

 

Test Clock. If Test Enable is asserted, this signal acts as the Test Clock

 

 

 

signal.

 

 

 

 

ANDIS

54

I

This pin is multiplexed and can be used for one of the following:

(T4ADV)

 

 

Auto-Negotiation Disable. In repeater mode, the Auto-Negotiation operates

 

 

 

for management reasons. If this input signal is high, the Auto-Negotiation

 

 

 

operation will be disabled.

 

 

 

T4ADV. In DTE (adapter) mode, this pin enables the combo mode. This

 

 

 

allows the LISTAT and SLVTRI pins to be used as interface to the slave PHY.

 

 

 

 

SCRMBY

23

I

Scrambler/Descrambler Bypass. If SCRMBY is high, the scrambler/

 

 

 

descrambler of TP-PMD will be bypassed.

 

 

 

 

LPBK

2

I

Loopback. When the LPBK signal is high, the 82555 will perform a

 

 

 

diagnostic loopback function.

 

 

 

 

RPT

50

I

Repeater. When the RPT signal is high, the 82555 functions in repeater

 

 

 

mode. When this signal is low, the 82555 runs in DTE (adapter) mode.

 

 

 

 

TESTEN

21

I

Test. If the TESTEN signal is high, the 82555 enables the test ports.

 

 

 

 

Datasheet

11

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Page 14 Page 16
Contents 82555 10/100 Mbps LAN Physical Layer Interface Product FeaturesRevision Description Networking SiliconContents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps ModeMII TX Interface 10 Mbps ModeMedia Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Numbers and Labels Pin DefinitionsPin Types Clock PinsTwisted Pair Ethernet TPE Pins Media Independent Interface MII PinsMedia Access Control/Repeater Interface Control Pins External Bias Pins LED PinsMiscellaneous Control Pins Power and Ground Pins VCCVSS 100BASE-TX Transmit Blocks 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Clock GenerationInvalid 2 100BASE-TX Scrambler and MLT-3 Encoder3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding Diagram100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection Auto-Negotiation 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Link IntegrityAuto 10/100 Mbps Speed Selection Adapter Mode AddressesNetworking Silicon Datasheet 10BASE-T Receive Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Transmit Blocks10BASE-T Jabber Control Function 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Link Integrity10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example MDI Frame Structure Management Data InterfaceTransition Bits Name Description DefaultMDI Registers MDI Registers 010BASE-T Register 1 Status Register Bit DefinitionsRegister 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8100BASE-TX Register 17 82555 Special Control Bit Definitions150 Actled Liled Register 22 Receive Symbol Error Counter Bit DefinitionsPriority Technology Bit Setting TechnologyAuto-Negotiation Functionality DescriptionPriority Parallel Detect and Auto-NegotiationAuto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Scrambler Bypass Reset and Miscellaneous Test ModesReset LoopbackNumber Code Test Instruction Select Input to Tout Test Instruction CodingGeneral Operating Conditions Electrical Specifications and Timing ParametersDC Characteristics Absolute Maximum RatingsTotal supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC CharacteristicsAC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing ParametersRXC tri-stated a Repeater Mode Timing ParametersSquelch Test Timing Parameters Transmit Packet Timing ParametersReceive Packet Timing Parameters Jabber Timing ParametersAuto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters11.4.11 X1 Clock Specifications Reset Timing ParametersX1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification12.0 82555 Package Information Symbol Description Min Norm Max10.0
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