Sun Microsystems SME5224AUPA-400 manual Clock Signal Distribution

UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

.

Serial

Parallel

Clock

Generator

Clock

Divider

CPU_CLK

Module

Connector

	UDB-II
UPA_CLK0	Clock Buffer

UDB-II

			UPA_CLK1		UltraSPARC-II
UPA_CLK	Clock				CPU
	Buffer
		UPA_CLK2		UPA Device
		UPA_CLKx		UPA Device

Module Boundary

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM/TAG

Figure 3. Clock Signal Distribution

LOW VOLTAGE PECL

Two trace signals compose each clock: one positive signal and one negative signal. Each signal is 180-degrees out of phase with the other. Signal timing is referenced to when the positive LVPECL signal transitions from low to high at the cross-over point, when the negative signal transitions from high to low. The trace-pair are routed side-by-side and use parallel termination, (specific routing techniques are require).

CPU CLOCK INPUT

The PLL in the CPU doubles the clock frequency presented at its clock pin. So, for a 400 MHz core CPU clock frequency, the CPU_CLK signal is 200 MHz. Therefore, for the CPU, actions will appear to occur at both tran- sitions of the input CPU_CLK.

CLOCK TRACE DELAYS

The LVPECL propagation time is constant for all clock signals so all balancing is based on length rather than time. All LVPECL traces are striplines (dielectric and power planes top and bottom) with a fixed 180 ps per inch propagation time using the FR4, PCB Dielectric.

10 Sun Microsystems, Inc July 1999