Sun Microsystems SME5224AUPA-400 manual Data Buffer Description, External Cache Description

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UltraSPARC™-II CPU Module	Advanced Version
400 MHz CPU, 4.0 MB E-Cache	SME5224AUPA-400

DATA BUFFER DESCRIPTION

UltraSPARC-II Data Buffer (UDB-II)

The UltraSPARC™-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a UPA Interconnect system bus width of 128 Data + 16 ECC.

There is a bidirectional ﬂow of information between the external cache of the CPU and the 144-bit UPA inter- connect. The information ﬂow is linked through the UDB-II, it includes: cache ﬁll requests, writeback data for dirty displaced cache lines, copyback data for cache entries requested by the system, non-cacheable loads and stores, and interrupt vectors going to and from the CPU.

Each UDB-II has a 64-bit interface plus eight parity bits on the CPU side, and a 64-bit interface plus eight error correction code (ECC) bits on the system side.

The CPU side of the UDB-II is clocked with the same clock delivered to UltraSPARC-II (1/2 of the CPU pipe- line frequency).

EXTERNAL CACHE DESCRIPTION

The external cache is connected to the E-cache data bus. Nine SRAM chips are used to implement the four megabyte cache. One SRAM is used as the tag SRAM and eight are used as data SRAMs. The tag SRAM is 128K x 36, while the data SRAMs are 256K x 18. All nine SRAMs operate in synchronous register-latch mode.

The SRAM interface to the CPU runs at one-half of the frequency of the CPU pipeline. The SRAM signals operate at 1.9V HSTL. The SRAM clock is a differential low-voltage HSTL input. [1]

1.PECL (Positive Emitter Coupled Logic) clocks are converted on the module to the HSTL clocks, for the E-cache interface.

July 1999

Sun Microsystems, Inc

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Contents Performance Module Features Module BeneﬁtsModule Description Ease of System DesignCPU Features CPU Beneﬁts CPU DescriptionUltraSPARC-II CPU Data Buffer Description External Cache DescriptionUltraSPARC-II Data Buffer UDB-II Module Component Overview Block DiagramUPA Connector Pins System InterfaceUPA Interconnect Module Power Module IDJtag Interface Clock Interface Signal DescriptionSignal Type Name and Function System InterfaceMiscellaneous Signals JTAG/Debug InterfaceInitialization Interface Tested CPU to UPA Module ClocksSystem Clocks System Clock DistributionClock Signal Distribution Absolute Maximum Ratings Electrical CharacteristicsSymbol Parameter Rating Units Symbol Parameter Min Typ Max UnitsDC Characteristics Module Power ConsumptionSymbol Parameter Conditions Min Typ Max Units Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice ModelClock Buffers Setup and Hold Time SpeciﬁcationsUpaclk Module Clocks Cpuclk Module ClockPropagation Delay, Output Hold Time Speciﬁcations Timing Measurement WaveformsMin Max Unit CPU Module Components Mechanical SpecificationsCPU Module Side View Two Step Approach to Thermal Design Thermal SpecificationsTerm Deﬁnition Speciﬁcation Comments Thermal Deﬁnitions and SpeciﬁcationsAir Velocity Temperature Estimating and Measuring MethodsAirﬂow Cooling Measurement Method Air Velocity SpeciﬁcationsHeatsink Temperature Measuring Method Case Temperature Measuring MethodAC Characteristics Jtag Timing MHz CPU MHz TCK Symbol Parameter Signals ConditionsJtag Testability Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP ViewVddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom ViewStorage and Shipping Specification Handling CPU ModulesValue Parameter Conditions Min Typ Date Document No Change Ordering InformationDocument Revision History Part Number CPU Speeds DescriptionSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc