Sun Microsystems SME5224AUPA-400 manual Module ID

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UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

Module ID

Module IDs are used to conﬁgure the UPA address of a module. The UPA_PORT_ID[4:3] are hardwired on the module to “0”. UPA_PORT_ID[1:0] are brought out to the connector pins. Each module is hardwired in the system to a ﬁxed and unique UPA address. This feature supports systems with four or fewer processors. For systems that need to support eight modules, UPA_SPEED[1] is connected to SYSID[2] in UDB-II to pro- vide UPA_PORT_ID[2].

Systems which support more than eight modules must map the limited set of UPA_PORT_IDs from this mod- ule to the range of required UPA_PORT_IDs, by implementation-speciﬁc means in the system.

System ﬁrmware (Open Boot Prom) uses UPA_CONFIG_REG[42:39] for generating correct clocks to the CPU module and the UPA system ASICs. These bits are hardwired on the module and are known at MCAP[3:0] at the UltraSPARC-II pins. The 4-bit MCAP value for this module is 0111b.

Module Power

Two types of power are required for this module: VDD at 3.3V, and VDD_CORE at 2.6V. The VDD_CORE supplies the DC-DC regulator which in turn supplies 1.9 volts to the core of the processor chip, the UDB-II external cache

interface I/O, and the SRAM I/O. A resistor located on the module sends the program value to the power supply so it generates VDD_CORE at 2.6V to the regulator.

JTAG Interface

The JTAG TCK signal is distributed to UDB-II, SRAMs and the CPU. For additional information about the JTAG interface, see "JTAG Testability," on page 22, and "JTAG (IEEE 1149.1) Timing," on page 23.

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Sun Microsystems, Inc

July 1999

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Contents Ease of System Design Module Features Module BeneﬁtsModule Description PerformanceCPU Description CPU Features CPU BeneﬁtsUltraSPARC-II CPU External Cache Description Data Buffer DescriptionUltraSPARC-II Data Buffer UDB-II Block Diagram Module Component OverviewSystem Interface UPA Connector PinsUPA Interconnect Module ID Module PowerJtag Interface System Interface Signal DescriptionSignal Type Name and Function Clock InterfaceJTAG/Debug Interface Miscellaneous SignalsInitialization Interface System Clock Distribution Module ClocksSystem Clocks Tested CPU to UPAClock Signal Distribution Symbol Parameter Min Typ Max Units Electrical CharacteristicsSymbol Parameter Rating Units Absolute Maximum RatingsModule Power Consumption DC CharacteristicsSymbol Parameter Conditions Min Typ Max Units UPA Data Bus Spice Model Module System Loading Example for UPADATA, UpaeccCpuclk Module Clock Setup and Hold Time SpeciﬁcationsUpaclk Module Clocks Clock BuffersTiming Measurement Waveforms Propagation Delay, Output Hold Time SpeciﬁcationsMin Max Unit Mechanical Specifications CPU Module ComponentsCPU Module Side View Thermal Specifications Two Step Approach to Thermal DesignThermal Deﬁnitions and Speciﬁcations Term Deﬁnition Speciﬁcation CommentsAir Velocity Speciﬁcations Temperature Estimating and Measuring MethodsAirﬂow Cooling Measurement Method Air VelocityCase Temperature Measuring Method Heatsink Temperature Measuring MethodMHz CPU MHz TCK Symbol Parameter Signals Conditions AC Characteristics Jtag TimingJtag Testability Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View PinUPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1Handling CPU Modules Storage and Shipping SpecificationValue Parameter Conditions Min Typ Part Number CPU Speeds Description Ordering InformationDocument Revision History Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc