Sun Microsystems SME5224AUPA-400 manual UltraSPARC -II CPU Module

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	SME5224AUPA-400
	July 1999
	UltraSPARC™ -II CPU Module
DATASHEET	400 MHz CPU, 4.0 MB E-Cache

MODULE DESCRIPTION

The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400) delivers high performance computing in a compact design. Based on the UltraSPARC™-II CPU, this module is designed using a small form factor board with an integrated external cache. It connects to the high bandwidth Ultra™ Port Architec- ture UPA bus via a high speed sturdy connector. The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, can plug into any UPA connector, saving system design costs and reducing the production time for new systems.

Heatsinks are attached to components on the module board. The module board is encased in a plastic shroud. The purpose of this shroud is to protect the components and channel airﬂow. Module design is geared towards ease of upgrade and ﬁeld support.

Module Features	Module Beneﬁts
Ease of System Design
	• Small form factor board with integrated external cache
	and UPA interface
	• JTAG boundary scan and performance instrumentation
	• PCB provides a multi-power plane bypass, reducing
	systemboard design requirements
Performance
	• High performance UltraSPARC™ CPU at 400MHz
	• Four megabytes of external cache using high speed
	register-latch SRAMs
	• Dedicated high bandwidth bus to processor
Glueless MP Support	•
	• Implements the high performance AUPA interface

Simplify System Qualiﬁcations by Complying with Industry and Government Standards

•Supports up to 16 Mbyte of external cache in a four-way MP system

•Backwards compatibility with systems implementing a UPA interface

•Plastic shroud protects components and channels airﬂow

•Multi-layer PCB controls EMI radiation

•Edge connectors and ejectors

•Small form factor board encased in a heat resistant shroud

•On-board voltage regulator accepts 2.6 volts for the Vdd_core; compatible with existing systems

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Contents Module Description Module Features Module BeneﬁtsEase of System Design PerformanceUltraSPARC-II CPU CPU Features CPU BeneﬁtsCPU Description UltraSPARC-II Data Buffer UDB-II Data Buffer DescriptionExternal Cache Description Module Component Overview Block DiagramUPA Interconnect UPA Connector PinsSystem Interface Jtag Interface Module PowerModule ID Signal Type Name and Function Signal DescriptionSystem Interface Clock InterfaceInitialization Interface Miscellaneous SignalsJTAG/Debug Interface System Clocks Module ClocksSystem Clock Distribution Tested CPU to UPAClock Signal Distribution Symbol Parameter Rating Units Electrical CharacteristicsSymbol Parameter Min Typ Max Units Absolute Maximum RatingsSymbol Parameter Conditions Min Typ Max Units DC CharacteristicsModule Power Consumption Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice ModelUpaclk Module Clocks Setup and Hold Time SpeciﬁcationsCpuclk Module Clock Clock BuffersMin Max Unit Propagation Delay, Output Hold Time SpeciﬁcationsTiming Measurement Waveforms CPU Module Components Mechanical SpecificationsCPU Module Side View Two Step Approach to Thermal Design Thermal SpecificationsTerm Deﬁnition Speciﬁcation Comments Thermal Deﬁnitions and SpeciﬁcationsAirﬂow Cooling Measurement Method Temperature Estimating and Measuring MethodsAir Velocity Speciﬁcations Air VelocityHeatsink Temperature Measuring Method Case Temperature Measuring MethodJtag Testability AC Characteristics Jtag TimingMHz CPU MHz TCK Symbol Parameter Signals Conditions Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP ViewVddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom ViewValue Parameter Conditions Min Typ Storage and Shipping SpecificationHandling CPU Modules Document Revision History Ordering InformationPart Number CPU Speeds Description Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc