Sun Microsystems SME5224AUPA-400 manual UltraSPARC-II CPU

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UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

CPU DESCRIPTION

UltraSPARC-II CPU

The UltraSPARC™-II CPU is the second generation in the UltraSPARC™ s-series microprocessor family.

A complete implementation of the SPARC™ V9 architecture, it has binary compatibility with all previous ver- sions of the SPARC™ microprocessor family.

The UltraSPARC™-II CPU is designed as a cost effective, scalable and reliable solution for high-end worksta- tions and servers. Meeting the demands of mission critical enterprise computing, theUltraSPARC™-II CPU runs enterprise applications requiring high data throughput. It is characterized by a high integer and floating point performance: optimally accelerating application performance, especially multimedia applications.

Delivering high memory bandwidth, media processing and raw compute performance, the UltraSPARC™-II CPU incorporates innovative technologies which lower the cost of ownership.

CPU Features

CPU Benefits

Architecture

• 64-bit SPARC-V9 architecture increases the

 

network computing application’s performance

•Thirty-two 64-bit integer registers

• Allows applications to store data locally in the

 

register files

•Superscalar/Superpipelined

• Allows for multiple integer and floating point

 

execution units leading to higher application

 

performance

•High performance memory interconnect

•Built-in Multiprocessing Capability

•VIS multimedia accelerating instructions

•100% binary compatibility with previous versions of SPARC™

•Uses 0.25 micron technology and packaging

•Alleviating the bottleneck of bandwidth to main memory

•Delivering scalability at the system level, thus increasing the end user’s return on investment

•Reducing the system cost by eliminating the special purpose media processor

•Increasing the return on investment of software applications

•Enhanced processor performance with decreased power consumption, thus increasing the reliability of the microprocessor

Performance

•Integer

•

17.4(SPECint95)

•Floating Point

•

25.7 (SPECfp95)

•Bandwidth (BW) to main memory

• 1.6 Gbyte/sec (peak) with a 100MHz UPA

Unique Features

 

 

•Block load and store instructions

• Delivering high performance access to large

 

 

datasets across the network

•JTAG Boundary Scan and Performance

• Enabling UltraSPARC™ based systems to offer

Instrumentation

 

features such as: power management, automatic

 

 

error correction, and lower maintenance cost

2

Sun Microsystems, Inc

July 1999

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Contents Ease of System Design Module Features Module BenefitsModule Description PerformanceCPU Features CPU Benefits CPU DescriptionUltraSPARC-II CPU Data Buffer Description External Cache DescriptionUltraSPARC-II Data Buffer UDB-II Block Diagram Module Component OverviewUPA Connector Pins System InterfaceUPA Interconnect Module Power Module IDJtag Interface System Interface Signal DescriptionSignal Type Name and Function Clock InterfaceMiscellaneous Signals JTAG/Debug InterfaceInitialization Interface System Clock Distribution Module ClocksSystem Clocks Tested CPU to UPAClock Signal Distribution Symbol Parameter Min Typ Max Units Electrical CharacteristicsSymbol Parameter Rating Units Absolute Maximum RatingsDC Characteristics Module Power ConsumptionSymbol Parameter Conditions Min Typ Max Units UPA Data Bus Spice Model Module System Loading Example for UPADATA, UpaeccCpuclk Module Clock Setup and Hold Time SpecificationsUpaclk Module Clocks Clock BuffersPropagation Delay, Output Hold Time Specifications Timing Measurement WaveformsMin Max Unit Mechanical Specifications CPU Module ComponentsCPU Module Side View Thermal Specifications Two Step Approach to Thermal DesignThermal Definitions and Specifications Term Definition Specification CommentsAir Velocity Specifications Temperature Estimating and Measuring MethodsAirflow Cooling Measurement Method Air VelocityCase Temperature Measuring Method Heatsink Temperature Measuring MethodAC Characteristics Jtag Timing MHz CPU MHz TCK Symbol Parameter Signals ConditionsJtag Testability Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View PinUPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1Storage and Shipping Specification Handling CPU ModulesValue Parameter Conditions Min Typ Part Number CPU Speeds Description Ordering InformationDocument Revision History Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Specifications Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Definitions and Specifications Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc
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