Sun Microsystems SME5224AUPA-400 manual Propagation Delay, Output Hold Time Specifications

Page 43

UltraSPARC-II CPU Module

Advanced Version

400 MHz CPU, 4.0 MB E-Cache

SME5224AUPA-400

Setup and Hold Time Specifications

 

 

 

400 MHz CPU

 

 

 

 

100 MHz UPA

 

Symbol

Setup Signals and Hold Time Signals

Waveforms

Min

Max

Unit

tH

UPA_DATA [127:0]

1

0.4

ns

Hold time

UPA_ADDR [35:0]

1

0.4

ns

 

UPA_ADDR_VALID, UPA_REQ_IN [2:0],

 

 

 

 

 

UPA_SC_REQ_IN, UPA_DATA_STALL,

 

 

 

 

 

UPA_ECC_VALID, UPA_RESET_L, UPA_XIR_L

 

 

 

 

 

 

 

 

 

 

 

UPA_ECC [15:0]

1

0.4

ns

 

 

 

 

 

 

 

UPA_S_REPLY [3:0]

1

0.4

ns

 

 

 

 

 

 

The following table, "Propagation Delay, Output Hold Time Specifications," specifies the propagation delay and output hold times for the UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module with a 4 Mbyte E-cache.

Propagation Delay, Output Hold Time Specifications

 

 

 

400 MHz CPU

 

 

 

 

100 MHz UPA

 

Symbol

Clock-to-Out Signals and Output-Hold Signals

Waveforms

Min

Max

Unit

tP

UPA_DATA [127:0]

2

3.8

ns

Clock-to-

UPA_ADDR [35:0]

2

3.1

ns

Out

UPA_ADDR_VALID, UPA_P_REPLY[4:0],

 

 

 

 

 

UPA_REQ_OUT

 

 

 

 

 

 

 

 

 

 

 

UPA_ECC [15:0]

2

3.8

ns

 

 

 

 

 

 

tOH

UPA_DATA [127:0]

2

1.1

ns

Output-

UPA_ADDR [35:0]

2

1.1

ns

Hold

UPA_ADDR_VALID, UPA_P_REPLY[4:0]

 

 

 

 

 

UPA_ECC [15:0]

2

1.1

ns

 

 

 

 

 

 

Timing Measurement Waveforms

xx_CLKx_NEG

2.4V

xx_CLKx_NEG

 

 

 

 

 

2.4V

 

 

 

xx_CLKx_POS

Data Input

Data Input

tSU

tH

2.0V

 

tSU

tH

0.8V

 

1.6V

2.4V

2.0V

0.4V

2.4V

0.8V

0.4V

xx_CLKx_POS

Rising Edge Output

Falling Edge Output

tp

tOH

tp

tOH

2.0V

0.8V

1.6V

2.4V

2.0V

0.8V

0.4V

2.4V

0.4V

Waveforms 1

Waveforms 2

Figure 5. Timing Measurement Waveforms

July 1999

Sun Microsystems, Inc

15

Image 43
Contents Performance Module Features Module BenefitsModule Description Ease of System DesignCPU Description CPU Features CPU BenefitsUltraSPARC-II CPU External Cache Description Data Buffer DescriptionUltraSPARC-II Data Buffer UDB-II Module Component Overview Block DiagramSystem Interface UPA Connector PinsUPA Interconnect Module ID Module PowerJtag Interface Clock Interface Signal DescriptionSignal Type Name and Function System InterfaceJTAG/Debug Interface Miscellaneous SignalsInitialization Interface Tested CPU to UPA Module ClocksSystem Clocks System Clock DistributionClock Signal Distribution Absolute Maximum Ratings Electrical CharacteristicsSymbol Parameter Rating Units Symbol Parameter Min Typ Max UnitsModule Power Consumption DC CharacteristicsSymbol Parameter Conditions Min Typ Max Units Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice ModelClock Buffers Setup and Hold Time SpecificationsUpaclk Module Clocks Cpuclk Module ClockTiming Measurement Waveforms Propagation Delay, Output Hold Time SpecificationsMin Max Unit CPU Module Components Mechanical SpecificationsCPU Module Side View Two Step Approach to Thermal Design Thermal SpecificationsTerm Definition Specification Comments Thermal Definitions and SpecificationsAir Velocity Temperature Estimating and Measuring MethodsAirflow Cooling Measurement Method Air Velocity SpecificationsHeatsink Temperature Measuring Method Case Temperature Measuring MethodMHz CPU MHz TCK Symbol Parameter Signals Conditions AC Characteristics Jtag TimingJtag Testability Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP ViewVddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom ViewHandling CPU Modules Storage and Shipping SpecificationValue Parameter Conditions Min Typ Date Document No Change Ordering InformationDocument Revision History Part Number CPU Speeds DescriptionSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Specifications Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Definitions and Specifications Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc