Sun Microsystems SME5224AUPA-400 Thermal Specifications, Two Step Approach to Thermal Design

Page 18

UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

THERMAL SPECIFICATIONS

The maximum CPU operating frequency and I/O timing is reduced when the junction temperature (Tj) of the CPU device is raised. Airflow must be directed to the CPU heatsink to keep the CPU device cool. Correct air- flow maintains the junction temperature within its operating range. The airflow directed to the CPU is usually sufficient to keep the surrounding devices on the topside of the module cool, including the SRAMs and clock circuitry. The cooling of the backside SRAMs is less critical, but still requires airflow according to the specifi- cations found in the section "Airflow Bottomside," on page 20.

The CPU temperature specification is provided in terms of its junction temperature. It is related to the case temperature by the thermal resistance of the package and the power the CPU is dissipating.

The case temperature can be measured directly by a thermocouple probe, verifying that the CPU junction temperature is correctly maintained over the entire operating range of the system. This includes both the compute load and the environmental conditions for the system. If measuring the case temperature is prob- lematic, then, measure the heatsink temperature and calculate the junction temperature. Both approaches for calculating junction temperature are explained in this section. Irrespective of which method is used, accurate measurement is required.

Two Step Approach to Thermal Design

Step One determines the ducted airflow requirements based on the CPU power dissipation, the thermal char- acteristics of the CPU package, and the surrounding heatsink assembly.

See "Thermal Definitions and Specifications," on page 19 for the modules specifications. The specifications for the heatsinks are found in the table "Heatsink-to-Air Thermal Resistance," page 20.

Step Two verifies the cooling effectiveness of the design, by measuring the heatsink or case temperature and calculating the junction temperature. The junction temperature must not exceed the CPU specification. In addition, the lower the junction temperature, the higher the system reliability. The CPU temperature must be verified under a range of system compute loads and system environmental conditions, using one of the temperature measuring methods described herein.

18

Sun Microsystems, Inc

July 1999

Page 17 Page 19
Image 18
Page 17 Page 19
Contents Ease of System Design Module Features Module BenefitsModule Description PerformanceCPU Features CPU Benefits CPU DescriptionUltraSPARC-II CPU Data Buffer Description External Cache DescriptionUltraSPARC-II Data Buffer UDB-II Block Diagram Module Component OverviewUPA Connector Pins System InterfaceUPA Interconnect Module Power Module IDJtag Interface System Interface Signal DescriptionSignal Type Name and Function Clock InterfaceMiscellaneous Signals JTAG/Debug InterfaceInitialization Interface System Clock Distribution Module ClocksSystem Clocks Tested CPU to UPAClock Signal Distribution Symbol Parameter Min Typ Max Units Electrical CharacteristicsSymbol Parameter Rating Units Absolute Maximum RatingsDC Characteristics Module Power ConsumptionSymbol Parameter Conditions Min Typ Max Units UPA Data Bus Spice Model Module System Loading Example for UPADATA, UpaeccCpuclk Module Clock Setup and Hold Time SpecificationsUpaclk Module Clocks Clock BuffersPropagation Delay, Output Hold Time Specifications Timing Measurement WaveformsMin Max Unit Mechanical Specifications CPU Module ComponentsCPU Module Side View Thermal Specifications Two Step Approach to Thermal DesignThermal Definitions and Specifications Term Definition Specification CommentsAir Velocity Specifications Temperature Estimating and Measuring MethodsAirflow Cooling Measurement Method Air VelocityCase Temperature Measuring Method Heatsink Temperature Measuring MethodAC Characteristics Jtag Timing MHz CPU MHz TCK Symbol Parameter Signals ConditionsJtag Testability Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View PinUPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1Storage and Shipping Specification Handling CPU ModulesValue Parameter Conditions Min Typ Part Number CPU Speeds Description Ordering InformationDocument Revision History Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Specifications Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Definitions and Specifications Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc
Top Page Image Contents