Sun Microsystems SME5224AUPA-400 manual Storage and Shipping Specification, Handling CPU Modules

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UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

STORAGE AND SHIPPING SPECIFICATION

			Value
Parameter	Conditions	Min.	Typ.	Max	Unit
Temperature	Ambient	-40	–	90	°C

Temperature ramp	Ambient	–	–	10	°C/min.

Shock (shipping)	Drop height on to any edge, corner, or side of	–	–	21	inches
- single module package	shipping box

Shock(shipping)	Drop height on to any edge, corner, or side of	–	–	18	inches
- multi-module package	shipping box

HANDLING CPU MODULES

CAUTION: Handle a module by carefully holding it by its edges and by the large CPU heatsink. Do not bump or handle the SRAM heatsinks because this action can cause unseen damage to the solder connections. Always handle modules and other electronic devices in an ESD-controlled environment.

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Sun Microsystems, Inc

July 1999

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Contents Ease of System Design Module Features Module BeneﬁtsModule Description PerformanceUltraSPARC-II CPU CPU Features CPU BeneﬁtsCPU Description UltraSPARC-II Data Buffer UDB-II Data Buffer DescriptionExternal Cache Description Block Diagram Module Component OverviewUPA Interconnect UPA Connector PinsSystem Interface Jtag Interface Module PowerModule ID System Interface Signal DescriptionSignal Type Name and Function Clock InterfaceInitialization Interface Miscellaneous SignalsJTAG/Debug Interface System Clock Distribution Module ClocksSystem Clocks Tested CPU to UPAClock Signal Distribution Symbol Parameter Min Typ Max Units Electrical CharacteristicsSymbol Parameter Rating Units Absolute Maximum RatingsSymbol Parameter Conditions Min Typ Max Units DC CharacteristicsModule Power Consumption UPA Data Bus Spice Model Module System Loading Example for UPADATA, UpaeccCpuclk Module Clock Setup and Hold Time SpeciﬁcationsUpaclk Module Clocks Clock BuffersMin Max Unit Propagation Delay, Output Hold Time SpeciﬁcationsTiming Measurement Waveforms Mechanical Specifications CPU Module ComponentsCPU Module Side View Thermal Specifications Two Step Approach to Thermal DesignThermal Deﬁnitions and Speciﬁcations Term Deﬁnition Speciﬁcation CommentsAir Velocity Speciﬁcations Temperature Estimating and Measuring MethodsAirﬂow Cooling Measurement Method Air VelocityCase Temperature Measuring Method Heatsink Temperature Measuring MethodJtag Testability AC Characteristics Jtag TimingMHz CPU MHz TCK Symbol Parameter Signals Conditions Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View PinUPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1Value Parameter Conditions Min Typ Storage and Shipping SpecificationHandling CPU Modules Part Number CPU Speeds Description Ordering InformationDocument Revision History Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc