Sun Microsystems SME5224AUPA-400 manual System Interface

Page 35

UltraSPARC™-II CPU Module

Advanced Version

400 MHz CPU, 4.0 MB E-Cache

SME5224AUPA-400

SIGNAL DESCRIPTION [1]

System Interface

Signal

Type

Name and Function

UPA_ADDR[35:0]

I/O

Packet switched transaction request bus. Maximum of three other masters and one

 

 

system controller can be connected to this bus. Includes 1-bit odd-parity protection.

 

 

Synchronous to UPA_CLK.

 

 

 

UPA_ADDR_VALID

I/O

Bidirectional radial UltraSPARC-II Bus signal between the UltraSPARC-II CPU and the

 

 

system. Driven by UltraSPARC-II to initiate UPA_ADDR transactions to the system.

 

 

Driven by system to initiate coherency, interrupt or slave transactions to

 

 

UltraSPARC-II CPU. Synchronous to UPA_CLK. Active high.

 

 

 

UPA_REQ_IN[2:0]

I

UltraSPARC-II system address bus arbitration request from up to three other

 

 

UltraSPARC-II bus ports, which may share the UPA_ADDR. Used by the

 

 

UltraSPARC-II for the distributed UPA_ADDR arbitration protocol. Connection to other

 

 

UltraSPARC-II bus ports is strictly dependent on the Master ID allocation.

 

 

Synchronous to UPA_CLK. Active high.

 

 

 

UPA_SC_REQ_IN

I

UltraSPARC-II system address bus arbitration request from the system. Used by the

 

 

UltraSPARC-II CPU for the distributed UPA_ADDR arbitration protocol.

 

 

Synchronous to UPA_CLK. Active high.

 

 

 

UPA_S_REPLY[4:0]

I

UltraSPARC-II system reply packet, driven by system controller to the UPA port.

 

 

Synchronous to UPA_CLK. Active high. UPA_S_REPLY [4] is a no-connect.

 

 

 

UPA_DATA_STALL

I

Driven by system controller to indicate whether there is a data stall. Active high.

 

 

 

UPA_P_REPLY[4:0]

O

UltraSPARC-II system reply packet, driven by the UltraSPARC-II to the system.

 

 

Synchronous to UPA_CLK. Active high.

 

 

 

UPA_DATA[127:0]

I/O

UPA Interconnect data bus.

 

 

 

UPA_ECC[15:0]

I/O

ECC bits for the data bus. 8-bit ECC per 64-bits of data.

 

 

 

UPA_ECC_VALID

I

Driven by the system controller to indicate that the ECC is valid for the data on the

 

 

UPA interconnect data bus: active high.

 

 

 

UPA_REQ_OUT

I/O

Arbitration request from this module: active high.

 

 

 

UPA_PORT_ID[1:0]

I

Module’s identification signals: active high. UPA_SPEED[1] acts as a

 

 

UPA_PORT_ID[2]

 

 

 

Clock Interface

Signal

Type

Name and Function

UPA_CLK[1:0]_POS

I

UPA Interconnect Clock: two copies are provided, one for the CPU and one for the

UPA_CLK[1:0]_NEG

 

UDBs

 

 

 

CPU_CLK_POS

I

Differential Clock inputs to the clock buffer on the module

CPU_CLK_NEG

 

 

 

 

 

UPA_RATIO

I

This is not used.

 

 

 

UPA_SPEED [0]

O

UPA_SPEED [0] is an output tied low on the module

 

 

 

UPA_SPEED [1]

I/O

UPA_SPEED[1] is tied low with 510 ohms and high to 3.3V with 4.7k ohms. It is

 

 

also connected to the SYSID [2] on each UDB-II.

 

 

 

UPA_SPEED [2]

O

UPA_SPEED [2] is tied low on the module

 

 

 

1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25.

July 1999

Sun Microsystems, Inc

7

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Contents Performance Module Features Module BenefitsModule Description Ease of System DesignUltraSPARC-II CPU CPU Features CPU BenefitsCPU Description UltraSPARC-II Data Buffer UDB-II Data Buffer DescriptionExternal Cache Description Module Component Overview Block DiagramUPA Interconnect UPA Connector PinsSystem Interface Jtag Interface Module PowerModule ID Clock Interface Signal DescriptionSignal Type Name and Function System InterfaceInitialization Interface Miscellaneous SignalsJTAG/Debug Interface Tested CPU to UPA Module ClocksSystem Clocks System Clock DistributionClock Signal Distribution Absolute Maximum Ratings Electrical CharacteristicsSymbol Parameter Rating Units Symbol Parameter Min Typ Max UnitsSymbol Parameter Conditions Min Typ Max Units DC CharacteristicsModule Power Consumption Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice ModelClock Buffers Setup and Hold Time SpecificationsUpaclk Module Clocks Cpuclk Module ClockMin Max Unit Propagation Delay, Output Hold Time SpecificationsTiming Measurement Waveforms CPU Module Components Mechanical SpecificationsCPU Module Side View Two Step Approach to Thermal Design Thermal SpecificationsTerm Definition Specification Comments Thermal Definitions and SpecificationsAir Velocity Temperature Estimating and Measuring MethodsAirflow Cooling Measurement Method Air Velocity SpecificationsHeatsink Temperature Measuring Method Case Temperature Measuring MethodJtag Testability AC Characteristics Jtag TimingMHz CPU MHz TCK Symbol Parameter Signals Conditions Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP ViewVddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom ViewValue Parameter Conditions Min Typ Storage and Shipping SpecificationHandling CPU Modules Date Document No Change Ordering InformationDocument Revision History Part Number CPU Speeds DescriptionSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Specifications Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Definitions and Specifications Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc
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