Sun Microsystems SME5224AUPA-400 manual Ordering Information

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UltraSPARC™-II CPU Module	Advanced Version
400 MHz CPU, 4.0 MB E-Cache	SME5224AUPA-400

ORDERING INFORMATION [1]

Part Number	CPU Speeds	Description
SME5224AUPA-400	400 MHz CPU	The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, features the UltraSPARC-II
		CPU at 400 MHz, a 4.0 Mbyte external cache, and two UDB-II data buffer ASICs.

1. To order the data sheet for this device use the document part number: 805-6390-05

DOCUMENT REVISION HISTORY

Date	Document No.	Change
July 1999	805-4835-05	This module is designed using the the UltraSPARC™–II, 400 MHz CPU,
		revision 3.x. See page 9, "Module Clocks," for changes effecting this version of
		the module.

May 1999	805-6390-04	Re-organization of the datasheet and update of speciﬁcations.

March 1999	805-6390-03	New section concerning the System Timing and Thermal Speciﬁcations.
	Preliminary Version	Revised speciﬁcations for DC characteristics and module power consumption.

December 1998	805-6390-02	Illustrations reﬂect a new heat sink design. Thermal section reﬂects the latest
	Advanced Version	heatsink design.

July 1999

Sun Microsystems, Inc

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Contents Performance Module Features Module BeneﬁtsModule Description Ease of System DesignCPU Description CPU Features CPU BeneﬁtsUltraSPARC-II CPU External Cache Description Data Buffer DescriptionUltraSPARC-II Data Buffer UDB-II Module Component Overview Block DiagramSystem Interface UPA Connector PinsUPA Interconnect Module ID Module PowerJtag Interface Clock Interface Signal DescriptionSignal Type Name and Function System InterfaceJTAG/Debug Interface Miscellaneous SignalsInitialization Interface Tested CPU to UPA Module ClocksSystem Clocks System Clock DistributionClock Signal Distribution Absolute Maximum Ratings Electrical CharacteristicsSymbol Parameter Rating Units Symbol Parameter Min Typ Max UnitsModule Power Consumption DC CharacteristicsSymbol Parameter Conditions Min Typ Max Units Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice ModelClock Buffers Setup and Hold Time SpeciﬁcationsUpaclk Module Clocks Cpuclk Module ClockTiming Measurement Waveforms Propagation Delay, Output Hold Time SpeciﬁcationsMin Max Unit CPU Module Components Mechanical SpecificationsCPU Module Side View Two Step Approach to Thermal Design Thermal SpecificationsTerm Deﬁnition Speciﬁcation Comments Thermal Deﬁnitions and SpeciﬁcationsAir Velocity Temperature Estimating and Measuring MethodsAirﬂow Cooling Measurement Method Air Velocity SpeciﬁcationsHeatsink Temperature Measuring Method Case Temperature Measuring MethodMHz CPU MHz TCK Symbol Parameter Signals Conditions AC Characteristics Jtag TimingJtag Testability Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP ViewVddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom ViewHandling CPU Modules Storage and Shipping SpecificationValue Parameter Conditions Min Typ Date Document No Change Ordering InformationDocument Revision History Part Number CPU Speeds DescriptionSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc