Sun Microsystems SME5224AUPA-400 manual UPA Data Bus Spice Model

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UltraSPARC™-II CPU Module	Advanced Version
400 MHz CPU, 4.0 MB E-Cache	SME5224AUPA-400

UPA Data Bus SPICE Model

A typical circuit for the UPA data bus and ECC signals is illustrated in Figure 4:.

Edge Connector

UDB-II Driver

Trace 1	3.1 nH
	Trace 2

1.0 pF 1.0 pF

via 0.6 pF

7 pF

0.5 nH 50 Ω 2 nH

Edge Connector

3.1 nH

Trace 3

1.0 pF 1.0 pF

Measure point for XB1

Trace 4

via 0.6 pF

0.5 nH 50 Ω

XB1 BGA Package Loading

Measure point for CPU

7 pF

2 nH

UDB-II of Second Module

Package Loading

Worst Case: Z0 = 60Ω, TP = 180 ps/inch, Trace 1 Length = 4.4”, Trace 2 Length = 0.6”, Trace 3 Length = 1.2”, Trace 4 Length = 4.4”

Best Case: Z0 = 50Ω, TP = 160 ps/inch, Trace 1 Length = 2.2”, Trace 2 Length = 0.2”, Trace 3 Length = 0.2”, Trace 4 Length = 2.2”

Figure 4. Module System Loading: Example for UPA_DATA, UPA_ECC

July 1999

Sun Microsystems, Inc

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Contents Module Description Module Features Module BeneﬁtsEase of System Design PerformanceCPU Description CPU Features CPU BeneﬁtsUltraSPARC-II CPU External Cache Description Data Buffer DescriptionUltraSPARC-II Data Buffer UDB-II Module Component Overview Block DiagramSystem Interface UPA Connector PinsUPA Interconnect Module ID Module PowerJtag Interface Signal Type Name and Function Signal DescriptionSystem Interface Clock InterfaceJTAG/Debug Interface Miscellaneous SignalsInitialization Interface System Clocks Module ClocksSystem Clock Distribution Tested CPU to UPAClock Signal Distribution Symbol Parameter Rating Units Electrical CharacteristicsSymbol Parameter Min Typ Max Units Absolute Maximum RatingsModule Power Consumption DC CharacteristicsSymbol Parameter Conditions Min Typ Max Units Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice ModelUpaclk Module Clocks Setup and Hold Time SpeciﬁcationsCpuclk Module Clock Clock BuffersTiming Measurement Waveforms Propagation Delay, Output Hold Time SpeciﬁcationsMin Max Unit CPU Module Components Mechanical SpecificationsCPU Module Side View Two Step Approach to Thermal Design Thermal SpecificationsTerm Deﬁnition Speciﬁcation Comments Thermal Deﬁnitions and SpeciﬁcationsAirﬂow Cooling Measurement Method Temperature Estimating and Measuring MethodsAir Velocity Speciﬁcations Air VelocityHeatsink Temperature Measuring Method Case Temperature Measuring MethodMHz CPU MHz TCK Symbol Parameter Signals Conditions AC Characteristics Jtag TimingJtag Testability Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP ViewVddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom ViewHandling CPU Modules Storage and Shipping SpecificationValue Parameter Conditions Min Typ Document Revision History Ordering InformationPart Number CPU Speeds Description Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc