Sun Microsystems SME5224AUPA-400 manual Upaclk Module Clocks

Page 42

UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

UPA AC TIMING SPECIFICATIONS

The UPA AC Timing Speciﬁcations are referenced to the UPA connector. The timing assumes that the clocks are correctly distributed, (see the section "System Clock Distribution," on page 9). The effective PCB clock trace lengths (CPU_CLK, UPA_CLK0 and UPA_CLK1) are used to calculate a balanced clock system.

UPA_CLK Module Clocks

All the UPA_CLKx trace pairs are the same length coming from the clock buffer and going to each load. To calculate UPA_CLK0 and UPA_CLK1 for the module, assume the trace lengths on the module are 9 inches, (which includes the module connector).

CPU_CLK Module Clock

The CPU_CLK trace on the system board is typically only a few inches long. It is the length of the traces used for the UPA_CLKs from the clock buffer plus the length of UPA_CLK from the clock divider to the clock buffer minus the effective trace length of CPU_CLK on the module, 18 inches, including the module connector.

Clock Buffers

The Clock buffer on the systemboard and the clock buffer on the module are assumed to have similar delays. The clock buffers have a 600 ps delay.

Timing References

The setup, hold and clock to output timing speciﬁcations are referenced at the module connector for the sig- nal and at the system UPA device pin. There is no reference point associated with the module since the module trace lengths provided above are effective lengths only and may not represent actual traces.

The following table speciﬁes the AC timing parameters for the UPA bus. For waveform illustrations see the illustration, "Timing Measurement Waveforms," on page 15.

Static signals consist of: UPA_PORT_ID[1:0], UPA_RATIO, and UPA_SPEED[2:0].

Setup and Hold Time Speciﬁcations

			400 MHz CPU
			100 MHz UPA
Symbol	Setup Signals and Hold Time Signals	Waveforms	Min	Max	Unit
tSU	UPA_DATA [127:0]	1	3.4	–	ns
Setup time	UPA_ADDR [35:0]	1	2.9	–	ns
	UPA_ADDR_VALID, UPA_REQ_IN [2:0],
	UPA_SC_REQ_IN, UPA_DATA_STALL,
	UPA_ECC_VALID, UPA_RESET_L, UPA_XIR_L

	UPA_ECC [15:0]	1	3.4	–	ns

	UPA_S_REPLY [3:0]	1	3.4	–	ns

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Sun Microsystems, Inc

July 1999

Image 42

Contents Ease of System Design Module Features Module BeneﬁtsModule Description PerformanceCPU Features CPU Beneﬁts CPU DescriptionUltraSPARC-II CPU Data Buffer Description External Cache DescriptionUltraSPARC-II Data Buffer UDB-II Block Diagram Module Component OverviewUPA Connector Pins System InterfaceUPA Interconnect Module Power Module IDJtag Interface System Interface Signal DescriptionSignal Type Name and Function Clock InterfaceMiscellaneous Signals JTAG/Debug InterfaceInitialization Interface System Clock Distribution Module ClocksSystem Clocks Tested CPU to UPAClock Signal Distribution Symbol Parameter Min Typ Max Units Electrical CharacteristicsSymbol Parameter Rating Units Absolute Maximum RatingsDC Characteristics Module Power ConsumptionSymbol Parameter Conditions Min Typ Max Units UPA Data Bus Spice Model Module System Loading Example for UPADATA, UpaeccCpuclk Module Clock Setup and Hold Time SpeciﬁcationsUpaclk Module Clocks Clock BuffersPropagation Delay, Output Hold Time Speciﬁcations Timing Measurement WaveformsMin Max Unit Mechanical Specifications CPU Module ComponentsCPU Module Side View Thermal Specifications Two Step Approach to Thermal DesignThermal Deﬁnitions and Speciﬁcations Term Deﬁnition Speciﬁcation CommentsAir Velocity Speciﬁcations Temperature Estimating and Measuring MethodsAirﬂow Cooling Measurement Method Air VelocityCase Temperature Measuring Method Heatsink Temperature Measuring MethodAC Characteristics Jtag Timing MHz CPU MHz TCK Symbol Parameter Signals ConditionsJtag Testability Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View PinUPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1Storage and Shipping Specification Handling CPU ModulesValue Parameter Conditions Min Typ Part Number CPU Speeds Description Ordering InformationDocument Revision History Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc