Sun Microsystems SME5224AUPA-400 Module Clocks, System Clocks, System Clock Distribution, 31, 51

Page 9

UltraSPARC™-II CPU Module

Advanced Version

400 MHz CPU, 4.0 MB E-Cache

SME5224AUPA-400

UPA AND CPU CLOCKS

Module Clocks

The module receives three differential pair low voltage PECL (LVPECL) clock signals (CPU_CLK, UPA_CLK0 and UPA_CLK1) from the systemboard and terminates them. The CPU_CLK is unique in the system, but the UPA_CLKs are two of many UPA clock inputs in the system.

The CPU_CLK operates at 1/2 the CPU core frequency. The UPA_CLKs operate at the UPA bus frequency. The CPU to UPA clock ratios refer to the CPU core to UPA bus clock signal frequency. The CPU on the module will automatically sense the clock ratio driven by the systemboard as long as the module clock timing is satisfied.

The UltraSPARC-II CPU and UDB-II data buffers detect and support multiple CPU to UPA clock frequency ratios. The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module is production tested in the 4:1 ratio (400 MHz CPU and 100 MHz UPA). It can be qualified at other ratios in specific systemboards.

 

Tested CPU to UPA

 

UltraSPARC-II CPU Module

Frequency Ratio

Other supported CPU to UPA Frequency Ratios

400 MHz, 4 Mbyte E-cache

4:1

3:1, 5:1, 6:1

 

 

 

System Clocks

The systemboard generates and distributes the CPU and UPA LVPECL clocks. The systemboard includes a frequency generator, frequency divider, clock buffers, and terminators.

The buffers fan-out the LVPECL clocks to the many UPA devices: the module, cross-bar data switches, system controller, FFB, and the system I/O bridge. The LVPECL clock trace pairs are routed source-to-destination. Each net is terminated at the destination. Most destinations are to single devices. The PCB traces for the LVPECL clocks are balanced to provide a high degree of synchronous UPA device operation.

System Clock Distribution

The goal of this clock distribution is to deliver a quality clock to each system UPA device simultaneously and with the correct clock relationships to the module clocks. For a discussion on how to layout and balance the systemboard LVPECL clock signals and UPA bus signals, see the UPA Electrical Bus Design Note (Document Part Number: 805-0089).

The effective length of the CPU_CLK, UPA_CLK0, and UPA_CLK1 clocks signals on the module are provided in the UPA AC Timing Specification section of this data sheet.

The block diagram for the LVPECL clocks "Clock Signal Distribution," on page 10, illustrates a typical system clock distribution network. Each clock line is a parallel-terminated, dual trace LVPECL clock signal for the CPU, the UPA and the SRAM devices.

July 1999

Sun Microsystems, Inc

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Contents Module Description Module Features Module BenefitsEase of System Design PerformanceCPU Features CPU Benefits CPU DescriptionUltraSPARC-II CPU Data Buffer Description External Cache DescriptionUltraSPARC-II Data Buffer UDB-II Module Component Overview Block DiagramUPA Connector Pins System InterfaceUPA Interconnect Module Power Module IDJtag Interface Signal Type Name and Function Signal DescriptionSystem Interface Clock InterfaceMiscellaneous Signals JTAG/Debug InterfaceInitialization Interface System Clocks Module ClocksSystem Clock Distribution Tested CPU to UPAClock Signal Distribution Symbol Parameter Rating Units Electrical CharacteristicsSymbol Parameter Min Typ Max Units Absolute Maximum RatingsDC Characteristics Module Power ConsumptionSymbol Parameter Conditions Min Typ Max Units Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice ModelUpaclk Module Clocks Setup and Hold Time SpecificationsCpuclk Module Clock Clock BuffersPropagation Delay, Output Hold Time Specifications Timing Measurement WaveformsMin Max Unit CPU Module Components Mechanical SpecificationsCPU Module Side View Two Step Approach to Thermal Design Thermal SpecificationsTerm Definition Specification Comments Thermal Definitions and SpecificationsAirflow Cooling Measurement Method Temperature Estimating and Measuring MethodsAir Velocity Specifications Air VelocityHeatsink Temperature Measuring Method Case Temperature Measuring MethodAC Characteristics Jtag Timing MHz CPU MHz TCK Symbol Parameter Signals ConditionsJtag Testability Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP ViewVddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom ViewStorage and Shipping Specification Handling CPU ModulesValue Parameter Conditions Min Typ Document Revision History Ordering InformationPart Number CPU Speeds Description Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Specifications Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Definitions and Specifications Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc
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