Sun Microsystems SME5224AUPA-400 manual Jtag Ieee 1149.1 Timing

Page 51

UltraSPARC™-II CPU Module	Advanced Version
400 MHz CPU, 4.0 MB E-Cache	SME5224AUPA-400

JTAG (IEEE 1149.1) TIMING

Clock

Data Input

2.0V

tSU

tH

1.5V

VIH

VIL

VIH

1.5V

VIL

Figure 10. Voltage Waveforms - Setup and Hold Times

		VIH
Clock		2.0V
		VIL
		tPD
	tOH	VOH
In-Phase		VOH
In-Phase		2.0V
Output		0.8V
		0.8V
		VOL
		tPD
	tOH	VOH
Out-of-Phase		VOH
Output		0.8V
		0.8V
		VOL

Figure 11. Voltage Waveforms - Propagation Delay Times

July 1999

Sun Microsystems, Inc

23

Image 51

Contents Performance Module Features Module BeneﬁtsModule Description Ease of System DesignCPU Features CPU Beneﬁts CPU DescriptionUltraSPARC-II CPU Data Buffer Description External Cache DescriptionUltraSPARC-II Data Buffer UDB-II Module Component Overview Block DiagramUPA Connector Pins System InterfaceUPA Interconnect Module Power Module IDJtag Interface Clock Interface Signal DescriptionSignal Type Name and Function System InterfaceMiscellaneous Signals JTAG/Debug InterfaceInitialization Interface Tested CPU to UPA Module ClocksSystem Clocks System Clock DistributionClock Signal Distribution Absolute Maximum Ratings Electrical CharacteristicsSymbol Parameter Rating Units Symbol Parameter Min Typ Max UnitsDC Characteristics Module Power ConsumptionSymbol Parameter Conditions Min Typ Max Units Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice ModelClock Buffers Setup and Hold Time SpeciﬁcationsUpaclk Module Clocks Cpuclk Module ClockPropagation Delay, Output Hold Time Speciﬁcations Timing Measurement WaveformsMin Max Unit CPU Module Components Mechanical SpecificationsCPU Module Side View Two Step Approach to Thermal Design Thermal SpecificationsTerm Deﬁnition Speciﬁcation Comments Thermal Deﬁnitions and SpeciﬁcationsAir Velocity Temperature Estimating and Measuring MethodsAirﬂow Cooling Measurement Method Air Velocity SpeciﬁcationsHeatsink Temperature Measuring Method Case Temperature Measuring MethodAC Characteristics Jtag Timing MHz CPU MHz TCK Symbol Parameter Signals ConditionsJtag Testability Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP ViewVddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom ViewStorage and Shipping Specification Handling CPU ModulesValue Parameter Conditions Min Typ Date Document No Change Ordering InformationDocument Revision History Part Number CPU Speeds DescriptionSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc