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Serial
Parallel
Clock
Generator
Clock
Divider
CPU_CLK
Module
Connector
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| UPA_CLK1 |
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UPA_CLK |
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Module Boundary
SRAM |
SRAM |
SRAM |
SRAM |
SRAM |
SRAM |
SRAM |
SRAM |
SRAM/TAG |
Figure 3. Clock Signal Distribution
LOW VOLTAGE PECL
Two trace signals compose each clock: one positive signal and one negative signal. Each signal is
CPU CLOCK INPUT
The PLL in the CPU doubles the clock frequency presented at its clock pin. So, for a 400 MHz core CPU clock frequency, the CPU_CLK signal is 200 MHz. Therefore, for the CPU, actions will appear to occur at both tran- sitions of the input CPU_CLK.
CLOCK TRACE DELAYS
The LVPECL propagation time is constant for all clock signals so all balancing is based on length rather than time. All LVPECL traces are striplines (dielectric and power planes top and bottom) with a fixed 180 ps per inch propagation time using the FR4, PCB Dielectric.
10 | Sun Microsystems, Inc | July 1999 |