Sun Microsystems SME5224AUPA-400 manual Clock Signal Distribution

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UltraSPARC-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

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Serial

Parallel

Clock

Generator

Clock

Divider

CPU_CLK

Module

Connector

 

UDB-II

UPA_CLK0

Clock Buffer

 

UDB-II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UPA_CLK1

 

 

 

 

UltraSPARC-II

 

UPA_CLK

 

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UPA_CLK2

 

 

 

 

 

 

UPA Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UPA_CLKx

 

 

 

 

 

 

UPA Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Module Boundary

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM/TAG

Figure 3. Clock Signal Distribution

LOW VOLTAGE PECL

Two trace signals compose each clock: one positive signal and one negative signal. Each signal is 180-degrees out of phase with the other. Signal timing is referenced to when the positive LVPECL signal transitions from low to high at the cross-over point, when the negative signal transitions from high to low. The trace-pair are routed side-by-side and use parallel termination, (specific routing techniques are require).

CPU CLOCK INPUT

The PLL in the CPU doubles the clock frequency presented at its clock pin. So, for a 400 MHz core CPU clock frequency, the CPU_CLK signal is 200 MHz. Therefore, for the CPU, actions will appear to occur at both tran- sitions of the input CPU_CLK.

CLOCK TRACE DELAYS

The LVPECL propagation time is constant for all clock signals so all balancing is based on length rather than time. All LVPECL traces are striplines (dielectric and power planes top and bottom) with a fixed 180 ps per inch propagation time using the FR4, PCB Dielectric.

10

Sun Microsystems, Inc

July 1999

Image 38
Contents Ease of System Design Module Features Module BenefitsModule Description PerformanceUltraSPARC-II CPU CPU Features CPU BenefitsCPU Description UltraSPARC-II Data Buffer UDB-II Data Buffer DescriptionExternal Cache Description Block Diagram Module Component OverviewUPA Interconnect UPA Connector PinsSystem Interface Jtag Interface Module PowerModule ID System Interface Signal DescriptionSignal Type Name and Function Clock InterfaceInitialization Interface Miscellaneous SignalsJTAG/Debug Interface System Clock Distribution Module ClocksSystem Clocks Tested CPU to UPAClock Signal Distribution Symbol Parameter Min Typ Max Units Electrical CharacteristicsSymbol Parameter Rating Units Absolute Maximum RatingsSymbol Parameter Conditions Min Typ Max Units DC CharacteristicsModule Power Consumption UPA Data Bus Spice Model Module System Loading Example for UPADATA, UpaeccCpuclk Module Clock Setup and Hold Time SpecificationsUpaclk Module Clocks Clock BuffersMin Max Unit Propagation Delay, Output Hold Time SpecificationsTiming Measurement Waveforms Mechanical Specifications CPU Module ComponentsCPU Module Side View Thermal Specifications Two Step Approach to Thermal DesignThermal Definitions and Specifications Term Definition Specification CommentsAir Velocity Specifications Temperature Estimating and Measuring MethodsAirflow Cooling Measurement Method Air VelocityCase Temperature Measuring Method Heatsink Temperature Measuring MethodJtag Testability AC Characteristics Jtag TimingMHz CPU MHz TCK Symbol Parameter Signals Conditions Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View PinUPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1Value Parameter Conditions Min Typ Storage and Shipping SpecificationHandling CPU Modules Part Number CPU Speeds Description Ordering InformationDocument Revision History Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Specifications Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Definitions and Specifications Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc