Sun Microsystems SME5224AUPA-400 manual Thermal Definitions and Specifications

Page 19

UltraSPARC-II CPU Module

Advanced Version

400 MHz CPU, 4.0 MB E-Cache

SME5224AUPA-400

Thermal Definitions and Specifications

Term

Definition

Specification

Comments

Tj

Maximum device

85 °C,

The Tj can't be measured directly by a thermo-couple

 

junction

 

probe. It must always be estimated as Tj or less. Less is

 

temperature

 

preferred.

 

 

 

 

Tc

Maximum case

76.7 °C

Measurable at the top-center of the device. Requires a hole

 

temperature

 

in the base of the heatsink to allow the thermocouple to be

 

 

 

in contact with the case. Maximum case temperature is

 

 

 

specified using a CPU device at its maximum power

 

 

 

dissipation.

 

 

 

 

Ts

Heatsink

75 °C

Measurable at the temperature of the base of the heatsink.

 

temperature

 

The best approach is to embed a thermocouple in a cavity

 

 

 

drilled in the heatsink base. An alternative approach is to

 

 

 

place the thermocouple between the fins/pins of the heat-

 

 

 

sink (insulated from the airflow) and in contact with the

 

 

 

base plate of the heatsink.

 

 

 

 

Ta

Module ambient air

see page 20

The air temperature as it approaches the heatsink.

 

temperature

 

 

 

 

 

 

Pd

Typical power

19.0 W

The worst case compute loads over the entire process

 

dissipation of the

 

range.

 

CPU

 

 

 

 

 

 

θjc

Maximum

0.5°C/W

The specification for the UltraSPARC™–II, 400 MHz CPU

 

junction-to-case

 

in a ceramic LGA package.

 

thermal resistance

 

 

 

of the package

 

 

 

 

 

 

θcs

Case-to-heatsink

0.1 °C/W

Accuracy of this value requires that good thermal contact is

 

thermal resistance

 

made between the package and the heatsink.

 

 

 

 

θsa

Heatsink-to-air

see page 20

This value is dependent on the heatsink design, the airflow

 

thermal resistance

 

direction, and the airflow velocity.

 

 

 

 

Va

Air velocity

see page 20

The ducted airflow.

 

 

 

 

July 1999

Sun Microsystems, Inc

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Contents Performance Module Features Module BenefitsModule Description Ease of System DesignCPU Description CPU Features CPU BenefitsUltraSPARC-II CPU External Cache Description Data Buffer DescriptionUltraSPARC-II Data Buffer UDB-II Module Component Overview Block DiagramSystem Interface UPA Connector PinsUPA Interconnect Module ID Module PowerJtag Interface Clock Interface Signal DescriptionSignal Type Name and Function System InterfaceJTAG/Debug Interface Miscellaneous SignalsInitialization Interface Tested CPU to UPA Module ClocksSystem Clocks System Clock DistributionClock Signal Distribution Absolute Maximum Ratings Electrical CharacteristicsSymbol Parameter Rating Units Symbol Parameter Min Typ Max UnitsModule Power Consumption DC CharacteristicsSymbol Parameter Conditions Min Typ Max Units Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice ModelClock Buffers Setup and Hold Time SpecificationsUpaclk Module Clocks Cpuclk Module ClockTiming Measurement Waveforms Propagation Delay, Output Hold Time SpecificationsMin Max Unit CPU Module Components Mechanical SpecificationsCPU Module Side View Two Step Approach to Thermal Design Thermal SpecificationsTerm Definition Specification Comments Thermal Definitions and SpecificationsAir Velocity Temperature Estimating and Measuring MethodsAirflow Cooling Measurement Method Air Velocity SpecificationsHeatsink Temperature Measuring Method Case Temperature Measuring MethodMHz CPU MHz TCK Symbol Parameter Signals Conditions AC Characteristics Jtag TimingJtag Testability Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP ViewVddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom ViewHandling CPU Modules Storage and Shipping SpecificationValue Parameter Conditions Min Typ Date Document No Change Ordering InformationDocument Revision History Part Number CPU Speeds DescriptionSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Specifications Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Definitions and Specifications Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc