Sun Microsystems SME5224AUPA-400 manual DC Characteristics, Module Power Consumption

Page 12

UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

DC Characteristics [1]

Symbol

Parameter

 

Conditions

Min

Typ

Max

Units

VOH

High-level output voltage

 

VDD = Min, IOH = Max

2.4

–

–

V

VIH

High-level input voltage, PECL clocks,

 

2.28

–

–

V

 

High-level input voltage,

 

 

 

2.0

–

–

V

 

except PECL clocks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIL

Low-level input voltage, PECL clocks

 

–

–

1.49

V

 

Low-level input voltage,

 

 

 

–

–

0.8

V

 

except PECL clocks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOL

Low-level output voltage

 

 

VDD = Min, IOL = Max

–

–

0.4

V

IDD

Supply current for VDD

[3]

 

VDD = Max, Freq.=Max

–

9.3

12.04

A

 

[2]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD_CORE

Supply current for VDD_CORE

[3]

VDD_CORE = Max, Freq.=Max

–

10.05

11.6

A

 

 

[4]

 

 

 

 

 

 

 

 

 

 

 

 

IOZ

High-impedance output current

VDD = Max, VO = 0.4V to 2.4V

–

–

30

μA

 

(Outputs without pull-ups)

 

 

–

–

-30

μA

 

 

 

 

 

 

 

 

High-impedance output current

VDD = Max, VO = VSS to VDD

–

–

250

μA

 

(Outputs with pull-ups)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

II

Input current (inputs without pull-ups)

VDD = Max, VI = VSS to VDD

–

–

± 20

μA

 

 

 

 

 

 

 

 

Input current (inputs with pull-ups)

VDD = Max, VI = VSS to VDD

–

–

-250

μA

 

 

 

 

 

 

 

 

 

IOH

High level output current

 

 

 

4

–

–

mA

IOL

Low level output current

 

 

 

8

–

–

mA

1.Note that this tables specifies the DC characteristics at the UPA 128M connector.

2.The supply current for the VDD includes the supply current for the CPU, UDB-II, and the SRAMs.

3.The typical DC current values represent the current drawn at nominal voltage with a typical, busy computing load. Variations in the device, computing load, and system implementation affect the actual current. The maximum DC current values will rarely, if ever, be exceeded running all known computing loads over the entire operating range. The maximum values are based on simulations.

4.The supply current for the VDD_CORE includes the supply current for the CPU, UDB-II, SRAMs, via the DC to DC regulator.

Module Power Consumption

This UltraSPARC-II module requires two supply voltages. The required voltages (provided to the module) for the VDD and VDD_CORE, are respectively 3.30V and 2.6V. The estimated maximum power consumption of the UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module (SME5224AUPA-400) is 70 watts at 400 MHz.

The estimated maximum power consumption includes the CPU, the SRAMs, the clock logic and the 8 watts consumed by the DC-DC regulator.

12

Sun Microsystems, Inc

July 1999

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Contents Module Features Module Benefits Module DescriptionEase of System Design PerformanceCPU Features CPU Benefits CPU DescriptionUltraSPARC-II CPU Data Buffer Description External Cache DescriptionUltraSPARC-II Data Buffer UDB-II Block Diagram Module Component OverviewUPA Connector Pins System InterfaceUPA Interconnect Module Power Module IDJtag Interface Signal Description Signal Type Name and FunctionSystem Interface Clock InterfaceMiscellaneous Signals JTAG/Debug InterfaceInitialization Interface Module Clocks System ClocksSystem Clock Distribution Tested CPU to UPAClock Signal Distribution Electrical Characteristics Symbol Parameter Rating UnitsSymbol Parameter Min Typ Max Units Absolute Maximum RatingsDC Characteristics Module Power ConsumptionSymbol Parameter Conditions Min Typ Max Units UPA Data Bus Spice Model Module System Loading Example for UPADATA, UpaeccSetup and Hold Time Specifications Upaclk Module ClocksCpuclk Module Clock Clock BuffersPropagation Delay, Output Hold Time Specifications Timing Measurement WaveformsMin Max Unit Mechanical Specifications CPU Module ComponentsCPU Module Side View Thermal Specifications Two Step Approach to Thermal DesignThermal Definitions and Specifications Term Definition Specification CommentsTemperature Estimating and Measuring Methods Airflow Cooling Measurement MethodAir Velocity Specifications Air VelocityCase Temperature Measuring Method Heatsink Temperature Measuring MethodAC Characteristics Jtag Timing MHz CPU MHz TCK Symbol Parameter Signals ConditionsJtag Testability Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View PinUPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1Storage and Shipping Specification Handling CPU ModulesValue Parameter Conditions Min Typ Ordering Information Document Revision HistoryPart Number CPU Speeds Description Date Document No ChangeSun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Specifications Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Definitions and Specifications Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc
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