Intel 8051 manuals
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When we buy new device such as Intel 8051 we often through away most of the documentation but the warranty.
Very often issues with Intel 8051 begin only after the warranty period ends and you may want to find how to repair it or just do some service work.
Even oftener it is hard to remember what does each function in Laptop Intel 8051 is responsible for and what options to choose for expected result.
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44 pages 5.84 Mb
8051 3 }-, }-. }~"'. {{ .m_ Architectural Specification and Functional Description Multiply in Up to Expandable Memory External with Compatible 8031 An - 8751 8031 -An 8051 -Control Oriented CPU With RAM and 803t 8031/8051/8751 SINGLE-COMPONENT 8-BIT MICROCOMPUTER I/O With Factory Mask- Programmable ROM MCS-80/MCS-85TM Peripherals to 128-Bytes Multiply, Divide, Subtract, Compare Most Instructions Execute and Divide r 8 I -"Lr-----A - 'l , , 2.1.2 On-Chip Peripheral Functions 8051 -Architectural Specification and Functional Description r-- ...... 9 => ~ '" 10 '" --~=-~l:'~>-"t"--r-\--J====j~:J 11 $ >----f ~~~~~ ii~O,.R ~ $ - Hn ___ ______________ L g:~~~~t.,.OR - - - >- 12 --r-r- :=fJ- -- -I I I _ 8051 Architectural Specification and Functional Description 13 ~. r-----14 8051 Architectural Specification and Functional Description 2.2.1 2.2 CPU HARDWARE Instruction Decoder 2.2.2 Program Counter 2.2.3 Internal Data Memory 8051 Architectural Specification and Functional Description 15 i G 2 1 ~ rr J~ ~L t1: '" '" '" ~"r ~~ - lr ~~~ i'.r I/t-- ~ ---0 w ~ f------------ t x + X L / E E V / N D P o I D I I I I 1 D D Figure 2.11. 8051 Family Functional Block Diagram 10 '" V l}, ~ 18 'F Architectural Specification and Functional Description ~: ~143 :~ I ~I: I 224 I 208 (DOH) I 19 8051 Architectural Specification and Functional Description DATA MANIPULATION 2.5 2.5.1 Data Transfer Operations 20 8051 Architectural Specification and Functional Description 2.5.2 Logic Operations 2.5.3 Arithmetic Operations " " 21 , , '" 8051 Architectural Specification and Functional Description 22 [:EJ r 1"'"4e-_-I-(~_--I~I_MM_E_D_'A_:r_E ::': 141---I/'-16---t1 What the Instruction Set INSTRUCTION 2.7 REG~~TER Architectural Specification and Functional Description REGIST:~~~DIRECT 23 I SeT 2.7.1 Is 2.7.2 24 ... 8051 Architectural Specification and Functional Description 25 o is ..... ,...:::.:-....,...I.,...;;:....,....;.,;....,.....;.;.;;.;..-r-..;.;.;..;..,.....;. 20 8051 26 The Architectural Specification and Functional Description 7.3 2. Operand Addressing Modes & Associated Operations 27 8051 Architectural Specification and Functional Description in 0 2.33.F. Figure Figure 2.33.C. Operand Addressing Single-Operand Operations Figure 2.33.D. Operand Addressing Two-Operand Operations Figure 2.33.E. Operand Addressing Two-Operand Operations 22 Operand Addressing Two-Operand Operations Figure 2.33.G. Operand Addressin'g Three-Operand Operations Figure 2.33.H. Operand AddreSSing FourmOperand Operations 2.8 INTERRUPT SYSTEM this address. In the 8051 there are five hardware resources that can generate an 2.34. A resource requests an interrupt by setting its associated interrupt request flag in the TCON or SCON register, as detailed Figure 2.35. The interrupt request will be 8051 Architectural Specification and Functional Description 28 .3 8051 Architectural Specification and Functional Description I/O AND 2.9 PORTS 29 2.8.1 PINS 30 8051 Architectural Specification and Functional Description EXTERNAL ACCESSING 2.10 MEMORY ArcnneCtural :specification and Functional Description 31 CD CD . 2.10.2 Accessing External Accessing External 2.10.1 Memory-Opera- tion of Ports Memory-Bus Cycle Timing G) Irl Figure 2.41. Program Memory Read Cycle 0 CD Figure 2.42. Data Memory Read Cycle >( V V V I D< I I I I I Figure 2.43. Data Memory Write Cycle Timing 27 I I 32 II @ II 33 CD CIT 2.11.2 2.11.1 2.11 CD 0. CD ' CD Architectural Specification and Functional Description 0. CD . ' ' . . . ' TIMER/COUNTER Timer/Counter Mode Selection Configuring the Timer/Counter Input 34 8051 Architectural Specification and Functional Description 2.12.1 2.11.3 Operation 2.11.4 Reading and Reloading the Timer/ Counters 2.12 SERIAL CHANNEL Serial Port Control and Data Buffer Registers 35 r----~ 36 8051 Architectural Specification and Functional Description 2.12.2 Operating Modes 8051 37 I Architectural Specification and Functional Description I I I I All 2.12.3 The Serial Frame I I 2.12.4 Transmission Rate Generation 2.12.5 UART Error Conditions 8051 Architectural Specification and Functional Description 2.13 EXTERNAL INTERFACE 2.13.1 Processor Reset and Initialization t .... ____ ---- ____ ------+I __ wro~~--------~~~~~I ___ ...... ---------i'- L 38 t 2.13.2 Power Down (Standby) Operation of Internal RAM rffl---- __ 39 WR Architectural Specification and Functional Description AS 8051 2.15 THE 2.14 EPROM PROGRAMMING AN EVOLUTION OF THE 8048 2.16 DEVELOPMENT SYSTEM AND SOFTWARE SUPPORT 8051 Software Development Package (ASM51 and CONV51) 8051 Macro Assembler (ASM51) BO.ard Architectural Specification and Functional OescripUon 8051 2.17 8051 Emulation 8048 to 8051 Assembly Converter Utility Program (CONV51) (EM-51) 8051 In-Circuit Emulator (ICE-51) Universal PROM Programmer Personality Card (UPP-851) 8051 Workshop INSITE Library FAMILY PIN DESCRIPTION 40 Vee Port 1 42 8051 Architectural Specification and Functional Description TABLE 2-1 8051 Corporation Intel copyrighted mnemonics All c.: SET INSTRUCTION SUMMARY
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