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8051 manual Architectural Specification
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8051
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Specs
Uart Error Conditions
Timer/Counter
Accessing External Memory
Ports and I/O Pins
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Architectural Specification
May 1980
©
INTEL CORPORATION, 1980.
AFN-01488A-01
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Contents
Architectural Specification
ICE
SINGLE-COMPONENT 8-BIT Microcomputer
Architectural Specification and Functional Description
Contents
Architectural Overview
Intelscomplete Line of SINGLE-CHIP Microcomputers
Abstract
Enhancing the 8048 ARCHITEC- Ture for the 80s
MACRO-VIEW of the 8051 Archi Tecture
On-Chip Peripheral Functions
Architectural Speciffcation ancrFunctionaJ Descrlpfion
Request
Microcomputer Expansion Components
Ii~O,.R~~~~~~
~ J -r-r ~r~ r =fJ
~~~--------~--~--~---I~
Architectural Specification and Functional Description
Program Counter
Instruction Decoder
Internal Data Memory
· t1
ProgramControl Section
Arithmetic Section
Oscillator and Timing Circuitry
Boolean Processor
Parallel I/O Ports
Operand Addressing
~~143 136 ~
Data Transfer Operations
Data Manipulation
18. External Data Memory Move Operations
Logic Operations
21. Internal Data Memory Logic Operations
Arithmetic Operations
REGplSCTER 14e--I-~--I~IMMEDArE,.j
Organization of the Instruction Set
Instruction SeT What the Instruction Set Is
Data Transfer
Control Transfer
33.A Operand Addressing Modes
Operand Addressing Modes & Associated Operations
MOV
Interrupt System
TFI TCON.7
External Interrupts
Ports and I/O Pins
Accessing External Memory
Accessing External Memory-Opera- tion of Ports
TsU~l ArcnneCtural specification and Functional Description
Accessing External Memory-Bus Cycle Timing
CDV
Timer/Counter Mode Selection
TIMER/COUNTER
Configuring the Timer/Counter Input
Serial Channel
47. Uart Interfacing Technique
SCON.O
Operating Modes
Serial Frame
Uart Error Conditions
Transmission Rate Generation
Power Down Standby Operation of Internal RAM
Processor Reset and Initialization
Eprom Programming
Vee
RSTNpD
8051 Instruction SET Summary
Instructions That Affect Flag Settings
All mnemonics copyrighted@ Intel Corporation