CHAPTER 2 ARCHITECTURAL OVERVIEW AND
| FUNCTIONAL DESCRIPTION (Continued) |
| |||
2.10 | Accessing External Memory | 25 | |||
| 2.10.1 Operation of Ports | 26 | |||
| 2.10.2 | Bus Cycle Timing | 26 | ||
2.11 | TimerlCounter | .......................... | 28 | ||
| 2.11.1 | TIC Mode Selection | 28 | ||
| 2.11.2 | Configuring the TIC Input | 28 | ||
| 2.11.3 | TIC Operation | 29 | ||
| 2.11.4 Reading and Reloading the TIC .... 29 | ||||
2.12 | Serial Channel | .......................... | 29 | ||
| 2.12.1 Serial Port Control Register and |
|
| ||
|
| Serial Data Registers | '.... | 31 | |
| 2.12.2 | Operating Modes | 31 | ||
|
| 2.12.2.1 | Operating Mode O•....•••. | 31 | |
|
| 2.12.2.2 | Operating Modes 1 |
|
|
|
|
| through 3 | 32 | |
| 2.12.3 The Serial Frame | 32 | |||
| 2.12.4 Transmission Rate Generation ..... 32 | ||||
| 2.12.5 UART Message Error Conditions ... 33 | ||||
2.13 | External Interface | 33 | |||
| 2.13.1 | Processor Reset and |
|
| |
|
| Initialization | 33 | ||
| 2.13.2 Power Down Operation of |
|
| ||
|
| Internal RAM | 33 | ||
2.14 | EPROM Programming | 34 | |||
2.15 | The 8051 as an Evolution of the 8048 | 34 |
2.16Development System and Software
| Support | 34 |
2.17 | 8051 Pin Description | 35 |
Table 2.1 | Instruction Set Summary | 37 |