Intel 8051 manual Interrupt System, Mov

Models: 8051

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8051 Architectural Specification and Functional Description

DIRECT Adchuing

-Opet'llnd

RAM (I11III 0-127) or SFA (I11III 128-255) RAM (0-127) or SFR (128-255)

REGISTER Addressing

Operand

C

A

R7oRO

DPTR

REGISTER-INDIRECT Acldrealng

-Opet'llnd

@R1. @RO [I•••• RAM (0-255)]

Note, SFR =Special Funcllon Regia'"

OperaUon

SETB.CLR.CPL

INC. DEC

Operation

SETB.CLR.CPL INC. DEC. DA, CLR. CPL. RL, RLC. RR. RRC.

SWAP INC. DEC INC

Operation

INC. DEC

REGISTER-INDIRECT. DIRECT Addressing

Operation

Operand 1

Operand 2

@R1, @RO[RAM (0-255)]

RAM or SFA

MOV

@SP [RAM (0-255)]

RAM or SFR

PUSH. POP

REGISTER-INDIRECT, REGISTER Addressing

Operation

Operand 1

Opera~2

@R1, @RO [RAM (0-255)]

A

MOV

@R1. @RO [EXT DATA (0-255)]

A

MOYX

@DPTR[EXT DATA(o-64K)]

A

MOYX

REGISTER-INDIRECT. IMMEDIATE Addressing

Operation

Operand 1

Opera~ 2

@R1, @RO [RAM (0-255)]

PM (immediate)

MOV

Figure 2.33.C. Operand Addressing Single-Operand Operations

DIRECT, DIRECT Ad~g

- Opet'llnd1

Operand 2

Operation

RAM or SFA

RAM or SFA

MOV

DIRECT. REGISTER Adchuing

Opet'llnd1

OperMCI 2

Operation

RAM (I11III) or SFR (bI")

C

MOV. ANL, ORL

C~RAM(IIIIII)

C

ANL,ORL

or SFR (I11III1

 

 

RAMorSFA

A

. MOV. ANL, ORL, XRL

RAM or SFR

RT-RD

MOV

DIRECT. REGISTER-INDIRECT AcIdreUIng

- Operand 1

- Operand 2

Operation

RAM or SFR

@R1. @RD

MOV

DIRECT. IMMEDIATE Addressing

- Opmmd1

OperMCl2

Operation

RAM or SFA

PM (ImmedI"')

MOV, ANL, ORL, XRL

Note: PM = Progr.... M....ory

 

 

Figure 2.33.F. Operand Addressing Two-Operand Operations

• REGISTER, BASE-REGISTERopIus-INDEX-REGISTER-INDIRECT AddressIng

Operand 1

Operand 2 •

-

Operand 3

. Opsrmlon

A

@ DPTR+A

 

MOVC

A

@PC+A

 

 

MOVC

PC

@ DPTR+A

 

JMP (IndINcI)

• REGISTER. IMMEDIATE, REGISTER-INDIRECT AddressIng

OperatIon

- Operand 1 -

Operand 2

-

Operand 3

PC

PM (Immediate)

 

@SP

LCALL,

 

 

 

 

ACALL

• REGISTER, IMMEDIATE, DIRECT AcIdeuIng

 

Oper~ 1

Operand 2

 

Operand 3

Opsrmlon

PC

PM

 

RAM (I11III) or

JB,JNB,

 

 

 

SFR(IIIIII)

JBC

PC

PM

 

RAM • SFA

DJNZ

• REGISTER, IMMEDIATE, REGISTER Addrasling

 

Operand'

Operand 2

 

Operand 3

0

PC

PM

 

C

JC,JNC

PC

PM

 

A

JZ.JNZ

PC

PM

 

RT-RO

DJNZ

Figure 2.33.D. Operand Addressing

Figure 2.33.G. Operand Addressin'g

Two-Operand Operations

Three-Operand Operations

• REGISTER, DIRECT Addressing

Operand 1

Operand 2

CRAM (bils) or SFR (bl")

ARAMorSFR

RT-RO

RAM or SFR

• REGISTER, REGISTER Addressing

Operand 1 Operand 2

AR7-RD

R7-RO A

AB

REGISTER, REGISTER-INDIRECT Addressing

Operand 1

Operand 2

A

@R1, @RO [RAM (0-255)]

A@Rl,@RO [EXT DATA (0-255)]

A

@OPTR [EXT DATA (o-64K)]

PC

@SP[RAM (0-255)]

• REGISTER, IMMEDIATE Addressing

Operand 1

Operand 2

A

PM (Immedlale)

R7-RO

PM (Immediate)

DPTR

PM (Immedlale)

PC

PM (Immediate)

Note: PM =Program Memory

Operalion

MOV

MOV, XCH. ADD, ADDC, SUBB,JI.NL,

ORL, XRL MOV

Operation

MOV, XCH, ADD, ADDC, SUBB,ANL,

ORL. XRL MOV MUL,DIV

Operation

MOV, XCH, ADD, ADDC, SUBB, ANL.

ORL, XRL, XCHD MOVX

MOVX

RET, RETI

Operation

MOV, ADD, ADDC, SUBB, ANL, ORL,

XRL

MOV

MOV WMP,AJMP,

SJMP

• REGISTER, IMMEDIATe, REGISTER. DIRECT AcIdnuIng

 

- Operand 1

- Operand 2

- Operand 3

- Operand 4

- Operation

PC

PM

A

RAM or SFA

CJNE

• REGISTER. IMMEDIATE. REGISTER. IMMEDIATE Addressing

-Operand 1 - Operand 2 - Oper~ 3 - Operand 4 - Operation

PC

PM

A

PM

CJNE

PC

PM

RT-RO

PM

CJNE

• REGISTER, IMMEDIATE, REGISTER-INDIRECT, IMMEDIATE Addressing

- Operand 1

- Operand 2

- Operand 3

- Operand 4

- Operation

PC

PM

@R1. @RO

PM

CJNE

Figure 2.33.H. Operand AddreSSing FourmOperand Operations

2.8 INTERRUPT SYSTEM

Interrupts result in a transfer of control to a new program location. The program servicing the request begins at this address. In the 8051 there are five hardware resources that can generate an interrupt request. The starting address of the interrupt service program for each interrupt source is shown in Figure 2.34.

Figure 2.33.E. Operand Addressing Two-Operand Operations

A resource requests an interrupt by setting its associated interrupt request flag in the TCON or SCON register, as detailed in Figure 2.35. The interrupt request will be

AFN-Ol488A-26

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Intel 8051 manual Interrupt System, Mov