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8051 Architectural Specification and Functional Description
T12
OSC
ALE
PORT 2
PORTO
ALE
FLOAT
| Figure 2.41. Program Memory Read Cycle Timing |
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CDV | \0 | I |
V |
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RD | ~0 |
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0
PORT 2 |
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| INST Irl FLOAT | 0 | 0 | (6) |
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PORTO | I FLOAT | >( | DATA IN | |||
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Figure 2.42. Data Memory Read Cycle Timing
ALE |
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PORT 2 |
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| IN IFLOAT | 0 | ~ |
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PORTO | INST | D< | DATA OUT | ||||
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NOTE: In Figures 2.42 and 2.43 the Prior and Subsequent Machine Cycles access Program Memory. |
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CD 1/
®
I ADDRESS
FLOAT ORFLOAT
I
II
@II
0
ADDRESS
OR FLOAT
Figure 2.43. Data Memory Write Cycle Timing
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