Texas Instruments TNETE100A manuals

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5Running TitleAttribute Reference
Preface
6Read This First
- ThunderLAN Programmers Guide
- About This Manual
- How to Use This Manual
- 7Notational Conventions
- Related Documentation
  - If You Need Assistance/ Trademarks
    - v
  - Read This First
- 8If You Need Assistance. ..
  - World-Wide Web Sites
  - North America, South America, Central America
  - Europe, Middle East, Africa
  - Asia-Pacific
  - Japan
  - Documentation
10Contents
14Figures
15Tables
18ThunderLAN Overview
- Chapter 1
  - 191.1 ThunderLAN Architecture
    - Figure 11. The ThunderLAN Controller
      - PCI Local Bus Specification,
  - 201.2 Networking Protocols
  - 211.3 PCI Interface
    - 1.3.1 PCI Cycles
    - 1.3.2 Byte Ordering
    - 22Figure 12. PCI Bus Byte Assignment
24ThunderLAN Registers
- Chapter 2
  - 252.1 Register Addresses
    - Figure 21. How ThunderLAN Registers are Addressed
      - PCI Configuration Space
  - 272.2 PCI Configuration Space
    - Figure 22. The PCI Configuration Space Registers
      - PCI Local Bus Specification.
      - PCI Local Bus Spec- ification,
      - PCI Local Bus Specification,
      - PCI Local Bus Specification
    - 28Figure 23. Configuration EEPROM Data Format
  - 322.3 Host Registers
    - Figure 24. Host Registers
      - Internal Registers
      - ThunderLAN Registers
  - 342.4 Internal Registers
    - Figure 25. Internal Registers
      - 35
      - ,
  - 382.5 MII PHY Registers
    - Figure 26. MII PHY Registers
      - 39,
        45to NetSio. Then the clock is cycled for each bit. The loop effectively cycles five times.
        To get an idle bit, turn off the data driver, then cycle the clock.
  - 482.6 External Devices
    - 2.6.1 BIOS ROM
    - 2.6.2 LEDs
    - 492.6.3 EEPROM
    - 2.6.4 ThunderLAN EEPROM Map
    - 53Table 21. ThunderLAN EEPROM Map
58Initializing and Resetting
- Chapter 3
  - 593.1 Initializing
    - 3.1.1 Finding the Network Interface Card (NIC)
    - 613.1.2 Finding the Controller in Memory and I/O Space
    - 623.1.3 Finding Which Interrupt was Assigned
      - PCI Local Bus Specification
    - 633.1.4 Turning on the I/O Port and Memory Address Decode
      - PCI Local Bus Specification.
    - 643.1.5 Recovering the Silicon Revision Value
    - 3.1.6 Setting the PCI Bus Latency Timer
  - 653.2 Resetting
    - 3.2.1 Hardware Reset
    - 663.2.2 Software Reset
68Interrupt Handling
- Chapter 4
  - 694.1 Loading and Unloading an Interrupt Service Routine (ISR)
  - 724.2 Prioritizing Adapter Interrupts
  - 734.3 Acknowledging Interrupts (Acking)
  - 744.4 Interrupt Type Codes
    - 4.4.1 No Interrupt (Invalid Code). Int_type = 000b
    - 4.4.2 Tx EOF Interrupt. Int_type = 001b
      - ThunderLAN Adaptive Performance Utilization Technical Brief
    - 754.4.3 Statistics Overflow Interrupt. Int_type = 010b
    - 4.4.4 Rx EOF Interrupt. Int_type = 011b
    - 4.4.5 Dummy Interrupt. Int_type = 100b
    - 764.4.6 Tx EOC Interrupt. Int_type = 101b
    - 4.4.7 Network Status Interrupt. Int_type = 110b and Int_Vec = 00h
    - 774.4.8 Adapter Check Interrupt. Int_type = 110b and Int_Vec 00h
      - Interrupt Type Codes
      - Interrupt Handling
    - 78Figure 41. Adapter Check Interrupt Fields
    - Table 41. Adapter Check Bit Definitions
      - Interrupt Type Codes
    - 79Table 42. Adapter Check Failure Codes
    - 80Table 43. Relevance of Error Status Bits for Adapter Check Failure Codes
      - 4.4.9 Rx EOC Interrupt. Int_type = 111b
82List Structures
- Chapter 5
  - List Management
  - 835.1 List Management
    - Some of the more commonly used list management terms are defined here:
    - Figure 51. List Pointers and Buffers
    - 84Figure 52. Linked List Management Technique
  - 865.2 CSTAT Field Bit Requirements
  - 875.3 One-Fragment Mode
  - 885.4 Receive List Format
    - Figure 53. Receive List Format One_Frag = 0
    - Figure 54. Receive List Format One_Frag = 1
    - 89Table 51. Receive Parameter List Fields
    - 90Figure 55. Receive
    - CSTAT Request Fields
    - Table 52.
    - Receive CSTAT Request Bits
    - 91Figure 56.
    - Receive CSTAT Complete
      - Interrupt Disable register
    - Fields
    - Table 53. Receive CSTAT Complete Bits
  - 925.5 Transmit List Format
    - Figure 57. Transmit List Format
    - 93Table 54. Transmit Parameter List Fields
    - 94Figure 58. Transmit CSTAT Request Fields
    - Table 55. Transmit CSTAT Request Bits
    - 95Figure 59. Transmit CSTAT Complete Fields
      - Interrupt Disable register
    - Table 56. Transmit CSTAT Complete Bits
96Transmitting and Receiving Frames
- Chapter 6
  - 976.1 Frame Format
    - 6.1.1 Receive (Rx) Frame Format
    - Figure 61. Token Ring Logical Frame Format (Rx)
    - Figure 62. Ethernet Logical Frame Format (Rx)
      - Frame Format
      - Transmitting and Receiving Frames
      - 6.1.2 Transmit (Tx) Frame Format
    - 98Figure 63. Token Ring Logical Frame Format (Tx)
    - Figure 64. Ethernet Logical Frame Format (Tx)
  - 996.2 GO Command
    - 6.2.1 Starting Frame Reception (Rx GO Command)
    - 1016.2.2 Starting Frame Transmission (Tx GO Command)
104Physical Interface (PHY)
- Chapter 7
  - 1057.1 MII-Enhanced Interrupt Event Feature
    - Figure 71. 100VG-AnyLAN Support Through ThunderLANs Enhanced 802.3u MII
      - MII-Enhanced Interrupt Event Feature
      - Physical Interface (PHY)
      - ThunderLAN implements the 19-signal MII shown in Table 71:
    - 106Table 71. ThunderLAN MII Pins (100M-bps CSMA/CD)
    - Figure 72. MII Frame Format: Read
    - 107Figure 73. MII Frame Format: Write
    - 108Table 72. Possible Sources of MII Event Interrupts
    - 109Figure 74. Assertion of Interrupt Waveform on the MDIO Line
    - Figure 75. Waveform Showing Interrupt Between MII Frames
  - 1117.3 Bit-Rate Devices
  - 1127.4 PHY Initialization
114Register Definitions
- 115A.1 PCI Configuration Registers
  - 116Figure A1. PCI Configuration Register Address Map
    - A.1.1 PCI Autoconfiguration from External 24C02 Serial EEPROM
  - 117Figure A2. Configuration EEPROM Data Format
    - A.1.2 PCI Vendor ID Register (@ 00h) Default = 104Ch
    - A.1.3 PCI Device ID Register (@ 02h) Default = 0500h
    - A.1.4 PCI Command Register (@ 04h)
  - 118Table A1. PCI Command Register Bits
    - A.1.5 PCI Status Register (@ 06h)
      - :
  - 119Table A2. PCI Status Register Bits
    - 121A.1.13 PCI Memory Base Address Register (@ 14h)
    - A.1.14 PCI BIOS ROM Base Address Register (@ 30h)
    - A.1.15 PCI NVRAM Register (@ 34h)
  - 122Table A3. PCI NVRAM Register Bits
    - A.1.16 PCI Interrupt Line Register (@ 3Ch)
    - A.1.17 PCI Interrupt Pin Register (@ 3Dh)
    - A.1.18 PCI Min_Gnt (@ 3Eh) and Max_Lat (@ 3Fh) Registers
    - A.1.19 PCI Reset Control Register (@ 40h)
  - 123Table A4. PCI Reset Control Register Bits
    - 124A.1.20 CardBus CIS Pointer (@ 28h)
- 125A.2 Adapter Host Registers
  - Figure A3. Host Interface Address Map
    - A.2.1 Host Command Register HOST_CMD @ Base_Address + 0 (Host)
  - CMD Register Bits
    - 130A.2.2 Channel Parameter Register CH_PARM @ Base_Address + 4 (Host)
    - A.2.3 Host Interrupt Register HOST_INT @ Base_Address + 10 (Host)
  - 131Table A6.
  - HOST_INT Register Bits
    - A.2.4 DIO Address Register DIO_ADR @ Base_Address + 8 (Host)
  - 132Table A7. DIO
  - ADR Register Bits
  - RAM Addressing
    - 133A.2.5 DIO Data Register DIO_DATA @ Base_Address + 12 (Host)
- 134A.3 Adapter Internal Registers
  - 135Figure A4. ADAPTER Internal Register Map
    - x
    - A.3.1 Network Command Register NetCmd @ 0x00 (DIO)
      - All bits in this register are set to 0 on an Ad_Rst or when PRST# is asserted.
  - 136Table A8. Network Command Register Bits
  - 137Table A8. Network Command Register Bits (Continued)
    - A.3.2 Network Serial I/O Register NetSio @ 0x00 (DIO)
  - Table A9. Network Serial I/O Register Bits
  - 138Table A9. Network Serial I/O Register Bits (Continued)
    - A.3.3 Network Status Register NetSts @ 0x00 (DIO)
      - All bits in this register are set to 0 on an Ad_Rst or when PRST# is asserted.
  - Table A10. Network Status Register Bits
  - 139Table A10. Network Status Register Bits (Continued)
    - A.3.4 Network Status Mask Register NetMask @ 0x00 (DIO)
  - Table A11. Network Status Mask Register Bits
    - A.3.5 Network Configuration Register NetConfig @ 0x04 (DIO)
  - 140Table A12. Network Configuration Register Bits
  - 141Table A12. Network Configuration Register Bits (Continued)
  - 142Table A13. MAC Protocol Selection Codes
    - A.3.6 Manufacturing Test Register ManTest @ 0x04 (DIO)
    - A.3.7 Default PCI Parameter Registers @ 0x08 0x0C (DIO)
  - Figure A5. Default PCI Parameter Register
    - 143A.3.8 General Address Registers Areg_0-3 @ 0x10 0x24 (DIO)
      - A.3.8.1 The All-Nodes Broadcast Address
      - A.3.8.2 Token Ring Frame Format Addressing Extensions
    - 144A.3.9 Hash Address Registers HASH1/HASH2 @ 0x28 0x2C (DIO)
    - A.3.10 Network Statistics Registers @ 0x30 0x40 (DIO)
  - 145Figure A6. Ethernet Error Counters
  - 146Table A14. Ethernet Error Counters
  - 147Figure A7. Demand Priority Error Counters
  - Table A15. Demand Priority Error Counters
    - A.3.11 Adapter Commit Register Acommit @ 0x40 (DIO) (Byte 3)
      - The adapter commit register indicates the PCI commit size of the adapter.
  - 148Table A16. Adapter Commit Register Bits
    - A.3.12 LED Register LEDreg @ 0x44 (DIO) (Byte 0)
    - A.3.13 Burst Size Register BSIZEreg @ 0x44 (DIO) (Byte 1)
  - 149Table A17. Burst Size Register Bits
    - 150A.3.14 Maximum Rx Frame Size Register MaxRx @ 0x44 (DIO) (Bytes 2 +3)
    - A.3.15 Interrupt Disable Register - INTDIS @ 0x48 (DIO) (BYTE 0)
  - 151Table A18. Demand Priority Error Counters
- 152A.4 10Base-T PHY Registers
  - Figure A8. 10Base-T PHY Registers
    - A.4.1 PHY Generic Control Register GEN_ctl @ 0x0
  - 153Table A19. PHY Generic Control Register Bits
  - 154Table A19. PHY Generic Control Register Bits (Continued)
    - A.4.2 PHY Generic Status Register GEN_sts @ 0x1
  - 155Table A20. PHY Generic Status Register Bits
  - 156Table A20. PHY Generic Status Register Bits (Continued)
    - 157A.4.3 PHY Generic Identifier GEN_id_hi/GEN_id_lo @ 0x2/0x3
    - A.4.4 Autonegotiation Advertisement Register AN_adv @ 0x4
  - 158Table A21. Autonegotiation Advertisement Register Bits
    - A.4.5 Autonegotiation Link Partner Ability Register AN_lpa @ 0x5
  - 159Table A22. Autonegotiation Link Partner Ability Register Bits
    - A.4.6 Autonegotiation Expansion Register AN_exp @ 0x6
  - 160Table A23. Autonegotiation Expansion Register Bits
    - A.4.8 ThunderLAN PHY Control Register TLPHY_ctl @ 0x11
  - 162Table A24. ThunderLAN PHY Control Register Bits
  - 163Table A24. ThunderLAN PHY Control Register Bits (Continued)
    - A.4.9 ThunderLAN PHY Status Register TLPHY_sts @ 0x12
  - Table A25. ThunderLAN PHY Status Register Bits
  - 164Table A25. ThunderLAN PHY Status Register Bits (Continued)
- 167B.1 100VG-AnyLAN Training
  - Figure B1. 802.12 Training Frame Format
  - 169Figure B2. Training Flowchart
- 171B.2 TNETE211 Register Descriptions
  - TNETE211 Register Descriptions
  - TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface
  - 172Figure B3. TNETE211 Registers
    - B.2.1 PHY Generic Control Register GEN_ctl @ 0x0
  - Table B1. PHY Generic Control Register Bits
  - 173Table B1. PHY Generic Control Register Bits (Continued)
    - B.2.2 PHY Generic Status Register GEN_sts @ 0x1
  - Table B2. PHY Generic Status Register Bits
  - 174Table B2. PHY Generic Status Register Bits (Continued)
    - B.2.3 PHY Generic Identifier GEN_id_hi/GEN_id_lo @ 0x2/0x3
    - B.2.4 ThunderLAN PHY Identifier High/Low TLPHY_id @ 0x10
    - B.2.5 ThunderLAN PHY Control Register TLPHY_ctl @ 0x11
  - 175Table B3. ThunderLAN PHY Control Register Bits
    - TNETE211 Register Descriptions
    - TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface
    - B.2.6 ThunderLAN PHY Status Register TLPHY_sts @ 0x12
  - 176Table B4. ThunderLAN PHY Status Register Bits
  - 177Table B4. ThunderLAN PHY Status Register Bits (Continued)