Adapter Host Registers

A.2 Adapter Host Registers

Host command registers contain bits which are toggled to tell the channel to use receive or transmit FIFOs. ThunderLAN's adapter host registers include the adapter internal registers (see section A.3, Adapter Internal Registers). The following subsections describe the functions of each host register accord- ing to protocol.

Figure A±3. Host Interface Address Map

 

 

 

 

Base address

31

16 15

0

offset

 

 

 

 

 

HOST_CMD

 

+0

 

CH_PARM

 

+4

 

 

 

 

 

HOST_INT

 

DIO_ADR

+8

 

 

 

 

 

 

DIO_DATA

 

+12

A.2.1 Host Command Register±HOST_CMD @ Base_Address + 0 (Host)

Byte 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte 2

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Go

 

Stop

 

Ack

 

 

 

 

Ch_Sel

 

 

 

EOC

R/T

Nes

0

 

0

Byte 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte 0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ad

 

Ld

 

Id

 

Req

Ints

Ints

Reserved

 

 

 

Ack Count

 

 

 

 

Rst

 

Tmr

 

Thr

 

Int

off

on

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table A±5. Host_CMD Register Bits

Bit

Name

Function

31

Go

Channel go: This command bit only affects the network channels.

 

 

if R/T = 0 (Tx GO):

 

 

Writing a 1 to this bit starts frame transmission on a stopped or inactive channel.

 

 

Ch_Parm contains the address of the first transmit list.

 

 

if R/T = 1 (Rx GO):

 

 

Writing a 1 to this bit starts frame reception on a stopped1 or inactive channel. Ch_Parm

 

 

contains the address of the first receive list.

 

 

Writing a 0 to this bit has no effect. This bit is always read as a 0.

1)Frame transmission and reception are always placed in the stopped (reset) state after reset. therefore, no frames are received into the Rx FIFO and no statistics are logged until the receiver has been started with a GO command.

A-12

Page 125
Image 125
Texas Instruments TNETE100A manual Adapter Host Registers, Host Command Register±HOSTCMD @ BaseAddress + 0 Host, Hostcmd

TNETE110A, TNETE211, TNETE100A specifications

Texas Instruments has been a leader in developing innovative semiconductor solutions, and their Ethernet PHY (Physical Layer Transceiver) family, specifically the TNETE100A, TNETE211, and TNETE110A, exemplifies this commitment to excellence. These devices are designed to address the needs of a variety of applications, ranging from industrial automation to consumer electronics.

The TNETE100A is a highly versatile Ethernet PHY capable of supporting 10/100 Mbps Ethernet connectivity. One of its main features is the low power consumption, which makes it an ideal choice for battery-operated devices. It incorporates advanced power management technologies, ensuring that the device operates efficiently while maintaining high performance. The TNETE100A also supports Auto-Negotiation, allowing for seamless communication between devices at different speeds, thereby enhancing flexibility in network configurations.

Moving to the TNETE211, this device supports 10/100/1000 Mbps Ethernet, making it suitable for high-speed networking applications. This PHY integrates features such as Energy Efficient Ethernet (EEE), which reduces power consumption during low-traffic periods, aligning with the contemporary demand for energy efficiency in networking equipment. The TNETE211 is engineered with robust EMI (Electromagnetic Interference) performance and provides multiple interface options, making it a versatile choice for embedded systems and networking applications.

The TNETE110A stands out in the lineup as a sophisticated device that supports both Fast Ethernet and Gigabit Ethernet. This PHY utilizes advanced signal processing techniques to ensure superior link robustness and performance in noisy environments. Its features include an integrated transformer driver, which simplifies PCB design and allows for compact device layouts. Additionally, the TNETE110A is designed to be fully compliant with Ethernet standards, ensuring reliable interoperability with other network components.

All three PHYs leverage Texas Instruments' expertise in integrated circuit design, resulting in low jitter and high signal integrity, essential for modern communication standards. They are optimized for a wide range of temperatures, making them suitable for harsh industrial applications. With built-in diagnostic capabilities, these devices also enable efficient fault detection and troubleshooting in network infrastructures.

In summary, the Texas Instruments TNETE100A, TNETE211, and TNETE110A are exemplary Ethernet PHY devices, each tailored to meet specific networking needs while adhering to stringent efficiency and performance criteria. Their advanced features, technologies, and reliability make them pivotal components in today's fast-paced digital landscape.