Adapter Internal Registers

A.3.10 Network Statistics Registers±@ 0x30±0x40 (DIO)

The network statistics registers gather frame error information. Registers vary in size, depending on the frequency with which they increment, and may be 8, 16, or 24 bits wide. Reading a statistics register clears its contents after the read. Byte reads to a multibyte register clear the contents of the bytes read only. As long as such registers are read in natural order (LSbyte first), no statis- tics will be lost, even when registers are read a byte at a time. Writing to a statis- tics register has no effect.

The MSBs of all the error counters are ORed together to create the statistics overflow interrupt vector (Int_type = 010) in the HOST_INT register. As more than one counter may have overflowed, all statistics registers must be read (cleared) on a statistics overflow interrupt.

Figure A±6. Ethernet Error Counters

DIO Address

Byte 3

Byte 2

Byte 1

Byte 0

 

 

 

 

 

0x30

Tx underrun

 

Good Tx frames

 

 

 

 

 

 

0x34

Rx overrun

 

Good Rx frames

 

 

 

 

 

 

0x38

Code error

CRC error

Deferred Tx

 

frames

frames

frames

 

 

 

 

 

0x3C

Single collision Tx frames

Multicollision Tx frames

 

 

 

 

 

0x40

 

Carrier loss

Late

Excessive

 

 

errors

collisions

collisions

 

 

 

 

 

A-32

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Texas Instruments TNETE110A, TNETE211 manual Network Statistics Registers±@ 0x30±0x40 DIO, Good Tx frames 0x34 Rx overrun
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TNETE110A, TNETE211, TNETE100A specifications

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