MII-Enhanced Interrupt Event Feature

Figure 7±3. MII Frame Format: Write

Start

Operation

PHY

Register

Turn-

Data

delimiter

code

address

address

around

 

 

 

 

 

 

01

01

AAAAA

RRRRR

10

DDDD DDDD DDDD DDDD

 

 

 

 

 

 

The clock cycle at the end of a transaction is used to disable the PMI from driv- ing the MDIO pin after a register read (the quiescent cycle). ThunderLAN sup- ports an extra feature on the serial management interface whereby the PHY can interrupt the host. The interrupt is signaled to the host on the MDIO pin one clock cycle later, during the half of the MDCLK cycle which is high.

MII-managed devices use this serial interface to access the internal register space as defined in the 802.3 or 802.12. A driver recognizes these devices by successfully reading the register space. A specific PHY can be found by read- ing the PHY identifier registers (locations 0x02h and 0x03h) and matching them to a known code.

For Texas Instruments PHYs and PMIs, these codes are shown below, where the xx denotes a revision:

-0x4000501xx for the internal 10Base-T PHY

-0x4000502xx for the TNETE211 100VG-AnyLAN PMI

One performance enhancement that ThunderLAN architecture supports is the ability to be interrupted by the PHY. This is accomplished through Thunder- LAN's enhanced MII. The MII-enhanced interface allows the PHY to interrupt the host system to indicate that the PHY needs some type of service, rather than requiring the host to constantly poll the MII registers.

The interrupt mechanism described here is an extension of the 802.3u stan- dard and does not affect MII compatibility with the existing 802.3u standard.

Servicing an interrupt typically requires the host to read the PHY generic status register followed by a read of the PHY specific status register. According to the 802.3u, the PHY-specific register is a user-defined register and is normally lo- cated between the MII registers 0x10 and 0x1f. Texas Instruments has chosen 0x12 as the location for the TLPHY_sts register.

The MII interrupt bit of this register, MINT, is bit 15, the MSB. This bit indicates that an interrupt is pending or has been cleared by the current read. The PHY- specific control register is located at 0x11 and contains two bits of importance, TINT (test interrupt) and INTEN (interrupt enable). The TINT bit is used to test the interrupt function; setting this bit forces the PHY to generate an interrupt. Clearing this bit disables this function. The function of the TINT bit is to test the

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Texas Instruments TNETE100A, TNETE211, TNETE110A manual ±3. MII Frame Format Write
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TNETE110A, TNETE211, TNETE100A specifications

Texas Instruments has been a leader in developing innovative semiconductor solutions, and their Ethernet PHY (Physical Layer Transceiver) family, specifically the TNETE100A, TNETE211, and TNETE110A, exemplifies this commitment to excellence. These devices are designed to address the needs of a variety of applications, ranging from industrial automation to consumer electronics.

The TNETE100A is a highly versatile Ethernet PHY capable of supporting 10/100 Mbps Ethernet connectivity. One of its main features is the low power consumption, which makes it an ideal choice for battery-operated devices. It incorporates advanced power management technologies, ensuring that the device operates efficiently while maintaining high performance. The TNETE100A also supports Auto-Negotiation, allowing for seamless communication between devices at different speeds, thereby enhancing flexibility in network configurations.

Moving to the TNETE211, this device supports 10/100/1000 Mbps Ethernet, making it suitable for high-speed networking applications. This PHY integrates features such as Energy Efficient Ethernet (EEE), which reduces power consumption during low-traffic periods, aligning with the contemporary demand for energy efficiency in networking equipment. The TNETE211 is engineered with robust EMI (Electromagnetic Interference) performance and provides multiple interface options, making it a versatile choice for embedded systems and networking applications.

The TNETE110A stands out in the lineup as a sophisticated device that supports both Fast Ethernet and Gigabit Ethernet. This PHY utilizes advanced signal processing techniques to ensure superior link robustness and performance in noisy environments. Its features include an integrated transformer driver, which simplifies PCB design and allows for compact device layouts. Additionally, the TNETE110A is designed to be fully compliant with Ethernet standards, ensuring reliable interoperability with other network components.

All three PHYs leverage Texas Instruments' expertise in integrated circuit design, resulting in low jitter and high signal integrity, essential for modern communication standards. They are optimized for a wide range of temperatures, making them suitable for harsh industrial applications. With built-in diagnostic capabilities, these devices also enable efficient fault detection and troubleshooting in network infrastructures.

In summary, the Texas Instruments TNETE100A, TNETE211, and TNETE110A are exemplary Ethernet PHY devices, each tailored to meet specific networking needs while adhering to stringent efficiency and performance criteria. Their advanced features, technologies, and reliability make them pivotal components in today's fast-paced digital landscape.
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