Adapter Internal Registers

 

Table A±9. Network Serial I/O Register Bits (Continued)

 

 

 

 

 

Bit

Name

Function

 

 

 

 

 

12

EDATA

EEPROM SIO data: This bit is used to read or write the state of the EDIO pin. When

 

 

 

ETXEN is set to 1, EDIO is driven with the value in this bit. When ETXEN is set to 0, this

 

 

 

bit is loaded with the value on the EDIO pin.

 

11

NMRST

MII not reset: This bit can be set to 1 or 0 by the DIO. This bit is set to 0 (active) by an

 

 

 

Ad_Rst or a PCI reset. The state of this bit directly controls the state of the MRST# (MII

 

 

 

reset) pin. If this bit is set to 0, the MRST# pin is asserted. If this bit is set to 1, the MRST#

 

 

 

pin is deasserted. This bit is not self-clearing and must be manually deasserted. It can

 

 

 

be set low and then immediately set high. Note that since every PHY attached to the MII

 

 

 

may not have a reset pin, you need to both do NMRST and individually reset each PHY.

 

10

MCLK

MII SIO clock: This bit controls the state of the MDCLK pin. When this bit is set to 1,

 

 

 

MDCLK is asserted. When this bit is set to 0, MDCLK is deasserted.

 

9

MTXEN

MII SIO transmit enable: This bit controls the direction of the MDIO pin. When this bit is

 

 

 

set to 1, MDIO is driven with the value in the MDATA bit. When this bit is set to 0, the

 

 

 

MDATA bit is loaded with the value on the MDIO pin.

 

8

MDATA

MII SIO data: This bit is used to read or write the state of the MDIO pin. When MTXEN

 

 

 

is set to 1, MDIO is driven with the value in this bit. When MTXEN is set to 0, this bit is

 

 

 

loaded with the value on the MDIO pin.

 

 

 

 

 

A.3.3 Network Status Register±NetSts @ 0x00 (DIO)

All bits in this register are set to 0 on an Ad_Rst or when PRST# is asserted.

 

 

 

Byte 2

 

 

 

 

23

22

21

20

 

19

18

17

16

MIRQ

HBEAT

TXSTOP

RXSTOP

 

 

Reserved

 

 

Table A±10. Network Status Register Bits

Bit

Name

Function

23

MIRQ

MII interrupt request: This bit is set whenever ThunderLAN detects that the MDIO pin

 

 

is asserted low and the MINTEN bit in the NetSio register is set. Assertion low of the

 

 

MDIO line between MII control frames is an indication from the PMI/PHY of an error or

 

 

a line status change.

 

 

This bit is cleared by writing a 1 to its bit position. Writing a 0 has no effect.

22

HBEAT

Heartbeat error: In CSMA/CD mode, a heartbeat interrupt is posted if MCOL is not as-

 

 

serted during the interframe gap following frame transmission. This bit is cleared by writ-

 

 

ing a 1 to its bit position. Writing a 0 has no effect.

21

TXSTOP

Transmitter stopped: This bit indicates the completion of a transmit STOP command.

 

 

This bit is cleared by writing a 1 to its bit position. Writing a 0 has no effect.

 

 

 

Register Definitions

A-25

Page 137 Page 139
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Image 138
Texas Instruments TNETE211, TNETE110A Network Status Register±NetSts @ 0x00 DIO, Table A±10. Network Status Register Bits
Page 137 Page 139

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