Adapter Host Registers

Table A±5. Host_CMD Register Bits (Continued)

Bit

Name

Function

29

Ack

Interrupt acknowledge: Writing a 1 to this bit acknowledges the interrupt indicated by

 

 

the Nes, EOC, Ch_Sel, and R/T fields.

 

 

if Nes = 0, EOC = 1, and R/T = 1 (Status Ack):

 

 

Writing a 1 to this bit acknowledges and clears the status interrupt.

 

 

if Nes = 0, EOC = 0, and R/T = 1 (Statistics Ack):

 

 

Writing a 1 to this bit acknowledges and clears the statistics interrupt.

 

 

if Nes = 1, EOC = 1, and R/T = 0 (Tx EOC Ack):

 

 

Writing a 1 to this bit acknowledges and clears a Tx EOC interrupt for the channel indi-

 

 

cated in Ch_Sel.

 

 

if Nes = 1, EOC = 1, and R/T = 1 (Rx EOC Ack):

 

 

Writing a 1 to this bit acknowledges and clears a Rx EOC interrupt for the channel indi-

 

 

cated in Ch_Sel.

 

 

if Nes = 1, EOC = 0, and R/T = 0 (Tx EOF Ack):

 

 

Writing a 1 to this bit acknowledges and clears 1 or more Tx EOF interrupts for the chan-

 

 

nel indicated in Ch_Sel, as indicated in the Ack Count field. If an attempt is made to ac-

 

 

knowledge more EOFs than the adapter has outstanding, an AckErr adapter check is

 

 

raised.

 

 

if Nes = 1, EOC = 0, and R/T = 1 (Rx EOF Ack):

 

 

Writing a 1 to this bit acknowledges and clears 1 or more Rx EOF interrupts for the chan-

 

 

nel indicated in Ch_Sel, as indicated in the Ack Count field. If an attempt is made to ac-

 

 

knowledge more EOFs than the adapter has outstanding, an AckErr adapter check is

 

 

raised.

 

 

Because of the internal calculations required in Tx EOF and Rx EOF acknowledges,

 

 

the HOST_INT register is not updated immediately. A short delay (six PCI cycles) is re-

 

 

quired before reading HOST_INT for such acknowledges to take effect.

 

 

Writing a 0 to this bit has no effect. This bit is always read as 0.

28±21

Ch_Sel

Channel select: This read/write field is used to select between channels on a multi-

 

 

channel adapter. This 8-bit field encodes the channel number (0 through 255). As this

 

 

adapter supports two channels, only the LSBs are implemented. All the MSBs (28

through 22) are hardwired to 0. This field is written in the same cycle as the command bits and allows a command to be issued in a single write cycle.

A-14

Page 127
Image 127
Texas Instruments TNETE110A, TNETE211, TNETE100A manual Cated in ChSel, If Nes = 1, EOC = 1, and R/T = 1 Rx EOC Ack, Raised

TNETE110A, TNETE211, TNETE100A specifications

Texas Instruments has been a leader in developing innovative semiconductor solutions, and their Ethernet PHY (Physical Layer Transceiver) family, specifically the TNETE100A, TNETE211, and TNETE110A, exemplifies this commitment to excellence. These devices are designed to address the needs of a variety of applications, ranging from industrial automation to consumer electronics.

The TNETE100A is a highly versatile Ethernet PHY capable of supporting 10/100 Mbps Ethernet connectivity. One of its main features is the low power consumption, which makes it an ideal choice for battery-operated devices. It incorporates advanced power management technologies, ensuring that the device operates efficiently while maintaining high performance. The TNETE100A also supports Auto-Negotiation, allowing for seamless communication between devices at different speeds, thereby enhancing flexibility in network configurations.

Moving to the TNETE211, this device supports 10/100/1000 Mbps Ethernet, making it suitable for high-speed networking applications. This PHY integrates features such as Energy Efficient Ethernet (EEE), which reduces power consumption during low-traffic periods, aligning with the contemporary demand for energy efficiency in networking equipment. The TNETE211 is engineered with robust EMI (Electromagnetic Interference) performance and provides multiple interface options, making it a versatile choice for embedded systems and networking applications.

The TNETE110A stands out in the lineup as a sophisticated device that supports both Fast Ethernet and Gigabit Ethernet. This PHY utilizes advanced signal processing techniques to ensure superior link robustness and performance in noisy environments. Its features include an integrated transformer driver, which simplifies PCB design and allows for compact device layouts. Additionally, the TNETE110A is designed to be fully compliant with Ethernet standards, ensuring reliable interoperability with other network components.

All three PHYs leverage Texas Instruments' expertise in integrated circuit design, resulting in low jitter and high signal integrity, essential for modern communication standards. They are optimized for a wide range of temperatures, making them suitable for harsh industrial applications. With built-in diagnostic capabilities, these devices also enable efficient fault detection and troubleshooting in network infrastructures.

In summary, the Texas Instruments TNETE100A, TNETE211, and TNETE110A are exemplary Ethernet PHY devices, each tailored to meet specific networking needs while adhering to stringent efficiency and performance criteria. Their advanced features, technologies, and reliability make them pivotal components in today's fast-paced digital landscape.