Texas Instruments TNETE211, TNETE110A, TNETE100A specification

10Base-T PHY Registers

A.4.8 ThunderLAN PHY Control Register±TLPHY_ctl @ 0x11

Byte 1															Byte 0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

IGLINK SWAPOL AUISEL SQEEN MTEST

Reserved

NFEW INTEN

TINT

Table A±24. ThunderLAN PHY Control Register Bits

Bit	Name	Function
15	IGLINK	Ignore link: When this bit is set to 0, the 10Base-T PHY expects to receive link pulses
		from the link partner (hub, switch, etc.), and sets the LINK bit in the GEN_sts register
		to 0 if they are not present. When this bit is set to 1, the internal link integrity test state
		machine is forced to stay in the link-good state, even when no link pulses are received.
		The LINK bit is set to 1.
14	SWAPOL	Swap polarity: Writing a 1 to this bit causes the PHY to reverse the polarity of the
		10Base-T receiver input pair. This is used to compensate for a cable in which the receive
		pair has been incorrectly wired.
13	AUISEL	AUI select: Writing a 1 to this bit causes the PHY to use the AUI network interface; writ-
		ing 0 (default) causes the PHY to use the 10Base-T network interface. The transmitters
		and receivers on the PHY are multiplexed between AUI and 10Base-T, so both cannot
		operate simultaneously.
12	SQEEN	SQE (signal quality error) enable: Writing a 1 to this bit causes the 10Base-T PHY to
		perform the SQE test function at the end of packet transmission. The SQE function is
		only performed in 10Base-T mode.
		The SQE test provides an internal simulated collision to test the collision detect circuitry.
		It asserts the MCOL bit between 600±1600 ns after the last positive edge of a frame
		is transmitted, with the collision lasting between 500 and 1500 ns.
11	MTEST	Manufacturing test: When this bit is set to a 1, the PHY is placed into manufacturing test
		mode. Manufacturing test mode is reserved for Texas Instruments manufacturing test
		only. Operation of the PHY and this register is undefined when this bit is set.
10±3	Reserved	Read and write as 0
2	NFEW	Not far end wrap: This bit only has meaning when the LOOPBK bit of the GEN_ctl is a

1.Writing a 1 to this bit causes the PHY to wrap the Tx data to the Rx data at the MII. Writing a 0 to this bit causes the PMI to wrap the Tx data to the Rx data at the furthest point possible. When NFEW is set to a 1, the preamble wraps without degradation; when it is set to a 0, the PHY needs only to wrap back the start of frame delimiter (SFD).

A-49

TNETE110A, TNETE211, TNETE100A specifications

Texas Instruments has been a leader in developing innovative semiconductor solutions, and their Ethernet PHY (Physical Layer Transceiver) family, specifically the TNETE100A, TNETE211, and TNETE110A, exemplifies this commitment to excellence. These devices are designed to address the needs of a variety of applications, ranging from industrial automation to consumer electronics.

The TNETE100A is a highly versatile Ethernet PHY capable of supporting 10/100 Mbps Ethernet connectivity. One of its main features is the low power consumption, which makes it an ideal choice for battery-operated devices. It incorporates advanced power management technologies, ensuring that the device operates efficiently while maintaining high performance. The TNETE100A also supports Auto-Negotiation, allowing for seamless communication between devices at different speeds, thereby enhancing flexibility in network configurations.

Moving to the TNETE211, this device supports 10/100/1000 Mbps Ethernet, making it suitable for high-speed networking applications. This PHY integrates features such as Energy Efficient Ethernet (EEE), which reduces power consumption during low-traffic periods, aligning with the contemporary demand for energy efficiency in networking equipment. The TNETE211 is engineered with robust EMI (Electromagnetic Interference) performance and provides multiple interface options, making it a versatile choice for embedded systems and networking applications.

The TNETE110A stands out in the lineup as a sophisticated device that supports both Fast Ethernet and Gigabit Ethernet. This PHY utilizes advanced signal processing techniques to ensure superior link robustness and performance in noisy environments. Its features include an integrated transformer driver, which simplifies PCB design and allows for compact device layouts. Additionally, the TNETE110A is designed to be fully compliant with Ethernet standards, ensuring reliable interoperability with other network components.

All three PHYs leverage Texas Instruments' expertise in integrated circuit design, resulting in low jitter and high signal integrity, essential for modern communication standards. They are optimized for a wide range of temperatures, making them suitable for harsh industrial applications. With built-in diagnostic capabilities, these devices also enable efficient fault detection and troubleshooting in network infrastructures.

In summary, the Texas Instruments TNETE100A, TNETE211, and TNETE110A are exemplary Ethernet PHY devices, each tailored to meet specific networking needs while adhering to stringent efficiency and performance criteria. Their advanced features, technologies, and reliability make them pivotal components in today's fast-paced digital landscape.

Texas Instruments TNETE211, TNETE110A, TNETE100A manual ThunderLAN PHY Control Register±TLPHYctl @

Models: TNETE110A TNETE211 TNETE100A

A.4.8 ThunderLAN PHY Control Register±TLPHY_ctl @ 0x11

Byte 1

Table A±24. ThunderLAN PHY Control Register Bits

Bit

IGLINK

SWAPOL

AUISEL

SQEEN

MTEST

NFEW

TNETE110A, TNETE211, TNETE100A specifications