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Running TitleAttribute Reference
Preface
Read This First
ThunderLAN Programmers Guide
About This Manual
How to Use This Manual
Notational Conventions
Related Documentation
If You Need Assistance/ Trademarks
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Contents
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Figures
Tables
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ThunderLAN Overview
Chapter 1
1.1 ThunderLAN Architecture
Figure 11. The ThunderLAN Controller
PCI Local Bus Specification,
1.2 Networking Protocols
1.3 PCI Interface
1.3.1 PCI Cycles
1.3.2 Byte Ordering
Figure 12. PCI Bus Byte Assignment
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ThunderLAN Registers
Chapter 2
2.1 Register Addresses
Figure 21. How ThunderLAN Registers are Addressed
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PCI Configuration Space
2.2 PCI Configuration Space
Figure 22. The PCI Configuration Space Registers
PCI Local Bus Specification.
PCI Local Bus Spec- ification,
PCI Local Bus Specification,
Figure 23. Configuration EEPROM Data Format
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2.3 Host Registers
Figure 24. Host Registers
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Internal Registers
ThunderLAN Registers
2.4 Internal Registers
Figure 25. Internal Registers
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2.5 MII PHY Registers
Figure 26. MII PHY Registers
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to NetSio. Then the clock is cycled for each bit. The loop effectively cycles five times.
To get an idle bit, turn off the data driver, then cycle the clock.
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2.6 External Devices
2.6.1 BIOS ROM
2.6.2 LEDs
2.6.3 EEPROM
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2.6.4 ThunderLAN EEPROM Map
Table 21. ThunderLAN EEPROM Map
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Initializing and Resetting
Chapter 3
3.1 Initializing
3.1.1 Finding the Network Interface Card (NIC)
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3.1.2 Finding the Controller in Memory and I/O Space
3.1.3 Finding Which Interrupt was Assigned
PCI Local Bus Specification
3.1.4 Turning on the I/O Port and Memory Address Decode
PCI Local Bus Specification.
3.1.5 Recovering the Silicon Revision Value
3.1.6 Setting the PCI Bus Latency Timer
3.2 Resetting
3.2.1 Hardware Reset
3.2.2 Software Reset
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Interrupt Handling
Chapter 4
4.1 Loading and Unloading an Interrupt Service Routine (ISR)
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4.2 Prioritizing Adapter Interrupts
4.3 Acknowledging Interrupts (Acking)
4.4 Interrupt Type Codes
4.4.1 No Interrupt (Invalid Code). Int_type = 000b
4.4.2 Tx EOF Interrupt. Int_type = 001b
ThunderLAN Adaptive Performance Utilization Technical Brief
4.4.3 Statistics Overflow Interrupt. Int_type = 010b
4.4.4 Rx EOF Interrupt. Int_type = 011b
4.4.5 Dummy Interrupt. Int_type = 100b
4.4.6 Tx EOC Interrupt. Int_type = 101b
4.4.7 Network Status Interrupt. Int_type = 110b and Int_Vec = 00h
4.4.8 Adapter Check Interrupt. Int_type = 110b and Int_Vec 00h
Interrupt Type Codes
Interrupt Handling
Figure 41. Adapter Check Interrupt Fields
Table 41. Adapter Check Bit Definitions
Interrupt Type Codes
Table 42. Adapter Check Failure Codes
Table 43. Relevance of Error Status Bits for Adapter Check Failure Codes
4.4.9 Rx EOC Interrupt. Int_type = 111b
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List Structures
Chapter 5
List Management
5.1 List Management
Some of the more commonly used list management terms are defined here:
Figure 51. List Pointers and Buffers
Figure 52. Linked List Management Technique
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5.2 CSTAT Field Bit Requirements
5.3 One-Fragment Mode
5.4 Receive List Format
Figure 53. Receive List Format One_Frag = 0
Figure 54. Receive List Format One_Frag = 1
Table 51. Receive Parameter List Fields
Figure 55. Receive
CSTAT Request Fields
Table 52.
Receive CSTAT Request Bits
Figure 56.
Receive CSTAT Complete
Interrupt Disable register
Fields
5.5 Transmit List Format
Figure 57. Transmit List Format
Table 54. Transmit Parameter List Fields
Figure 58. Transmit CSTAT Request Fields
Table 55. Transmit CSTAT Request Bits
Figure 59. Transmit CSTAT Complete Fields
Interrupt Disable register
Table 56. Transmit CSTAT Complete Bits
Transmitting and Receiving Frames
Chapter 6
6.1 Frame Format
6.1.1 Receive (Rx) Frame Format
Figure 61. Token Ring Logical Frame Format (Rx)
Figure 62. Ethernet Logical Frame Format (Rx)
Frame Format
6.1.2 Transmit (Tx) Frame Format
Figure 63. Token Ring Logical Frame Format (Tx)
Figure 64. Ethernet Logical Frame Format (Tx)
6.2 GO Command
6.2.1 Starting Frame Reception (Rx GO Command)
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6.2.2 Starting Frame Transmission (Tx GO Command)
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Physical Interface (PHY)
Chapter 7
7.1 MII-Enhanced Interrupt Event Feature
Figure 71. 100VG-AnyLAN Support Through ThunderLANs Enhanced 802.3u MII
MII-Enhanced Interrupt Event Feature
Physical Interface (PHY)
ThunderLAN implements the 19-signal MII shown in Table 71:
Table 71. ThunderLAN MII Pins (100M-bps CSMA/CD)
Figure 72. MII Frame Format: Read
Figure 73. MII Frame Format: Write
Table 72. Possible Sources of MII Event Interrupts
Figure 74. Assertion of Interrupt Waveform on the MDIO Line
Figure 75. Waveform Showing Interrupt Between MII Frames
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7.3 Bit-Rate Devices
7.4 PHY Initialization
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Register Definitions
A.1 PCI Configuration Registers
Figure A1. PCI Configuration Register Address Map
A.1.1 PCI Autoconfiguration from External 24C02 Serial EEPROM
Figure A2. Configuration EEPROM Data Format
A.1.2 PCI Vendor ID Register (@ 00h) Default = 104Ch
A.1.3 PCI Device ID Register (@ 02h) Default = 0500h
A.1.4 PCI Command Register (@ 04h)
Table A1. PCI Command Register Bits
A.1.5 PCI Status Register (@ 06h)
:
Table A2. PCI Status Register Bits
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A.1.13 PCI Memory Base Address Register (@ 14h)
A.1.14 PCI BIOS ROM Base Address Register (@ 30h)
A.1.15 PCI NVRAM Register (@ 34h)
Table A3. PCI NVRAM Register Bits
A.1.16 PCI Interrupt Line Register (@ 3Ch)
A.1.17 PCI Interrupt Pin Register (@ 3Dh)
A.1.18 PCI Min_Gnt (@ 3Eh) and Max_Lat (@ 3Fh) Registers
A.1.19 PCI Reset Control Register (@ 40h)
Table A4. PCI Reset Control Register Bits
A.1.20 CardBus CIS Pointer (@ 28h)
A.2 Adapter Host Registers
Figure A3. Host Interface Address Map
A.2.1 Host Command Register HOST_CMD @ Base_Address + 0 (Host)
CMD Register Bits
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A.2.2 Channel Parameter Register CH_PARM @ Base_Address + 4 (Host)
A.2.3 Host Interrupt Register HOST_INT @ Base_Address + 10 (Host)
Table A6.
HOST_INT Register Bits
A.2.4 DIO Address Register DIO_ADR @ Base_Address + 8 (Host)
Table A7. DIO
ADR Register Bits
RAM Addressing
A.2.5 DIO Data Register DIO_DATA @ Base_Address + 12 (Host)
A.3 Adapter Internal Registers
Figure A4. ADAPTER Internal Register Map
x
A.3.1 Network Command Register NetCmd @ 0x00 (DIO)
All bits in this register are set to 0 on an Ad_Rst or when PRST# is asserted.
Table A8. Network Command Register Bits
Table A8. Network Command Register Bits (Continued)
A.3.2 Network Serial I/O Register NetSio @ 0x00 (DIO)
Table A9. Network Serial I/O Register Bits
Table A9. Network Serial I/O Register Bits (Continued)
A.3.3 Network Status Register NetSts @ 0x00 (DIO)
All bits in this register are set to 0 on an Ad_Rst or when PRST# is asserted.
Table A10. Network Status Register Bits
Table A10. Network Status Register Bits (Continued)
A.3.4 Network Status Mask Register NetMask @ 0x00 (DIO)
Table A11. Network Status Mask Register Bits
A.3.5 Network Configuration Register NetConfig @ 0x04 (DIO)
Table A12. Network Configuration Register Bits
Table A12. Network Configuration Register Bits (Continued)
Table A13. MAC Protocol Selection Codes
A.3.6 Manufacturing Test Register ManTest @ 0x04 (DIO)
A.3.7 Default PCI Parameter Registers @ 0x08 0x0C (DIO)
Figure A5. Default PCI Parameter Register
A.3.8 General Address Registers Areg_0-3 @ 0x10 0x24 (DIO)
A.3.8.1 The All-Nodes Broadcast Address
A.3.8.2 Token Ring Frame Format Addressing Extensions
A.3.9 Hash Address Registers HASH1/HASH2 @ 0x28 0x2C (DIO)
A.3.10 Network Statistics Registers @ 0x30 0x40 (DIO)
Figure A6. Ethernet Error Counters
Table A14. Ethernet Error Counters
Figure A7. Demand Priority Error Counters
Table A15. Demand Priority Error Counters
A.3.11 Adapter Commit Register Acommit @ 0x40 (DIO) (Byte 3)
The adapter commit register indicates the PCI commit size of the adapter.
Table A16. Adapter Commit Register Bits
A.3.12 LED Register LEDreg @ 0x44 (DIO) (Byte 0)
A.3.13 Burst Size Register BSIZEreg @ 0x44 (DIO) (Byte 1)
Table A17. Burst Size Register Bits
A.3.14 Maximum Rx Frame Size Register MaxRx @ 0x44 (DIO) (Bytes 2 +3)
A.3.15 Interrupt Disable Register - INTDIS @ 0x48 (DIO) (BYTE 0)
Table A18. Demand Priority Error Counters
A.4 10Base-T PHY Registers
Figure A8. 10Base-T PHY Registers
A.4.1 PHY Generic Control Register GEN_ctl @ 0x0
Table A19. PHY Generic Control Register Bits
Table A19. PHY Generic Control Register Bits (Continued)
A.4.2 PHY Generic Status Register GEN_sts @ 0x1
Table A20. PHY Generic Status Register Bits
Table A20. PHY Generic Status Register Bits (Continued)
A.4.3 PHY Generic Identifier GEN_id_hi/GEN_id_lo @ 0x2/0x3
A.4.4 Autonegotiation Advertisement Register AN_adv @ 0x4
Table A21. Autonegotiation Advertisement Register Bits
A.4.5 Autonegotiation Link Partner Ability Register AN_lpa @ 0x5
Table A22. Autonegotiation Link Partner Ability Register Bits
A.4.6 Autonegotiation Expansion Register AN_exp @ 0x6
Table A23. Autonegotiation Expansion Register Bits
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A.4.8 ThunderLAN PHY Control Register TLPHY_ctl @ 0x11
Table A24. ThunderLAN PHY Control Register Bits
Table A24. ThunderLAN PHY Control Register Bits (Continued)
A.4.9 ThunderLAN PHY Status Register TLPHY_sts @ 0x12
Table A25. ThunderLAN PHY Status Register Bits
Table A25. ThunderLAN PHY Status Register Bits (Continued)
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B.1 100VG-AnyLAN Training
Figure B1. 802.12 Training Frame Format
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Figure B2. Training Flowchart
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B.2 TNETE211 Register Descriptions
TNETE211 Register Descriptions
TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface
Figure B3. TNETE211 Registers
B.2.1 PHY Generic Control Register GEN_ctl @ 0x0
Table B1. PHY Generic Control Register Bits
Table B1. PHY Generic Control Register Bits (Continued)
B.2.2 PHY Generic Status Register GEN_sts @ 0x1
Table B2. PHY Generic Status Register Bits
Table B2. PHY Generic Status Register Bits (Continued)
B.2.3 PHY Generic Identifier GEN_id_hi/GEN_id_lo @ 0x2/0x3
B.2.4 ThunderLAN PHY Identifier High/Low TLPHY_id @ 0x10
B.2.5 ThunderLAN PHY Control Register TLPHY_ctl @ 0x11
Table B3. ThunderLAN PHY Control Register Bits
TNETE211 Register Descriptions
TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface
B.2.6 ThunderLAN PHY Status Register TLPHY_sts @ 0x12
Table B4. ThunderLAN PHY Status Register Bits
Table B4. ThunderLAN PHY Status Register Bits (Continued)
