10Base-T PHY Registers

Table A±24. ThunderLAN PHY Control Register Bits (Continued)

Bit

Name

Function

1

INTEN

Interrupt enable: Writing a 1 to this bit allows the PHY to generate interrupts on the MII

 

 

if the MINT bit is set. Writing a 0 to this bit prevents the PHY from generating any MII

 

 

interrupts. This bit does not disable test interrupts.

0

TINT

Test interrupt: Writing a 1 to this bit causes the PHY to generate an interrupt on the MII.

 

 

Writing a 0 to this bit causes the PHY to stop generating an interrupt on the MII. This

 

 

test function is totally independent of the INTEN and MINT bits. This bit is used for diag-

 

 

nostic testing of the MII interrupt function.

 

 

 

A.4.9 ThunderLAN PHY Status Register±TLPHY_sts @ 0x12

Byte 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte 0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MINT

PHOK

POLOK

Reserved

Table A±25. ThunderLAN PHY Status Register Bits

Bit

Name

Function

15

MINT

MII interrupt: This bit indicates an MII interrupt condition. The MII interrupt request is

 

 

activated (and latched) until the register is read. Writing to this bit has no effect. This

 

 

bit is set to a 1 when:

-PHOK is set to 1

-LINK changes state or is different from either the last read value or the current state of the link

-RFLT is set to 1

-JABBER is set to 1

-PLOK is set to 1

-PAGERX is set to 1

-AUTOCMPLT is set to 1

-TPENERGY is set to 1

14

PHOK

Power high OK: This bit indicates that the internal crystal oscillator circuit has per-

 

 

formed 75 oscillations (cycles). PHY-sourced clocks (MRCLK and MTCLK) are not

 

 

valid until this bit is asserted. If a crystal is connected to FXTL1/FXTL2 rather than a

crystal oscillator, the clocks may take up to 50 ms to become stable and the PHY re- quires the RESET bit be set to ensure it is in a valid state. When the state of this bit changes, the PSTATE bit in the TLPHY_sts register is set.

A-50

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Texas Instruments TNETE110A ThunderLAN PHY Status Register±TLPHYsts @, Table A±25. ThunderLAN PHY Status Register Bits
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TNETE110A, TNETE211, TNETE100A specifications

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