Adapter Internal Registers

Table A±12. Network Configuration Register Bits (Continued)

Bit

Name

Function

12

RxCRC

Receive CRC: When this bit is set to 1, the ThunderLAN controller transfers frame CRC

 

 

to the host for received frames and includes it in the reported frame length. The value

 

 

in the MaxRx register must be large enough to accommodate the data field plus this

 

 

transferred CRC. Failure to do so may result in an Rx overrun

11

PEF

Pass error frames: When this bit is set to 1 and the CAF bit is set in NetCmd (copy all

 

 

frames mode), frames that would otherwise be rejected by the adapter due to CRC,

 

 

alignment, or coding errors are passed to the host. Such frames have the Rx_Error bit

 

 

in the list receive CSTAT set to differentiate them from good frames. This mode does not

 

 

affect adapter frame statistics.

10

One

One fragment mode: When this bit is set to 1, the adapter only reads a single fragment

 

fragment

(data count/data address pair) on the receive channel (rather than ten). When this bit

 

 

is set to 0, the adapter reads and uses up to ten fragments.

 

 

If multifragment mode is selected and less than ten fragments are used, the host must

 

 

write a 0 to the data count field of the fragment immediately after the last fragment used.

 

 

Generally, receive frames are not fragmented because they must be examined by host

 

 

software first. One fragment mode can be used in such cases, where it improves adapt-

 

 

er performance by reducing the number of PCI cycles needed to read the receive list.

9

One chn

One channel mode: When this bit is set to 1, the adapter only supports a single transmit

 

 

channel (rather than two). When this bit is set to 0, the adapter supports two transmit

 

 

channels.

 

 

The adapter has 3K bytes of FIFO RAM for frame buffering. In normal two-channel

 

 

mode, 1.5K is allocated to Rx (one Rx channel), and 1.5K to transmit (0.75K per Tx

 

 

channel). In one-channel mode, all 1.5K of Tx FIFO RAM is allocated to channel 0, the

 

 

only channel. In one-channel mode, the HOST_CMD bit operations on channel 1 are

 

 

ignored.

8

MTEST

Manufacturing test: When this bit is set to 1, the adapter is placed into manufacturing

 

 

test mode. Manufacturing test mode is reserved for Texas Instruments manufacturing

 

 

test. Operation of the adapter with this bit set is undefined.

7

PHY_En

On-chip PHY enable: This bit is used to enable/disable the adapter's on-chip 10Base-T

 

 

PHY. When this bit is set to 0, the on-chip PHY is disabled and placed in a powered-down

 

 

state. When this bit is set to a 1, the on-chip PHY is enabled as a potential PHY on the

 

 

shared MII (it still needs to be selected/configured using MDCLK/MDIO).²

6±0

MAC select

MAC protocol select: This field is used to select the network MAC protocol required. The

 

 

seven-bit code allows for 128 unique network configurations. This version of

 

 

ThunderLAN supports four protocol modes: CSMA/CD and three types of data stream

interfaces (supporting external demand priority and token ring implementations). Bits 6 through 2 are, therefore, hardwired to 0.

²If the on-chip PHY is selected as the active MII PHY, all MII pins except MDCLK and MDIO are disabled.

A-28

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Texas Instruments TNETE211, TNETE110A, TNETE100A manual Mtest
Page 140 Page 142

TNETE110A, TNETE211, TNETE100A specifications

Texas Instruments has been a leader in developing innovative semiconductor solutions, and their Ethernet PHY (Physical Layer Transceiver) family, specifically the TNETE100A, TNETE211, and TNETE110A, exemplifies this commitment to excellence. These devices are designed to address the needs of a variety of applications, ranging from industrial automation to consumer electronics.

The TNETE100A is a highly versatile Ethernet PHY capable of supporting 10/100 Mbps Ethernet connectivity. One of its main features is the low power consumption, which makes it an ideal choice for battery-operated devices. It incorporates advanced power management technologies, ensuring that the device operates efficiently while maintaining high performance. The TNETE100A also supports Auto-Negotiation, allowing for seamless communication between devices at different speeds, thereby enhancing flexibility in network configurations.

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All three PHYs leverage Texas Instruments' expertise in integrated circuit design, resulting in low jitter and high signal integrity, essential for modern communication standards. They are optimized for a wide range of temperatures, making them suitable for harsh industrial applications. With built-in diagnostic capabilities, these devices also enable efficient fault detection and troubleshooting in network infrastructures.

In summary, the Texas Instruments TNETE100A, TNETE211, and TNETE110A are exemplary Ethernet PHY devices, each tailored to meet specific networking needs while adhering to stringent efficiency and performance criteria. Their advanced features, technologies, and reliability make them pivotal components in today's fast-paced digital landscape.
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