MII-Enhanced Interrupt Event Feature

PHY interrupt function. The INTEN bit is used to enable and disable the PHY interrupt function. Setting the INTEN bit enables the PHY internal event sys- tem to generate interrupts; clearing the INTEN bit disables the PHY from gen- erating interrupts. Interrupts from the PHY are usually generated upon a change in status that requires an interrupt indication.

Typical interrupt-generating events are shown in Table 7±2:

Table 7±2. Possible Sources of MII Event Interrupts

Name

Function

Link

Interrupt generated when the last read value is different from

 

the current state of the link, or different from the latched link

 

fail value if the link went OK-FAIL-OK with no register read in

 

between.

TxJabber

Interrupt generated when the JABBER bit is changed from a

 

0 to a 1.

Remote fault

Interrupt generated when the remote fault (RFLT) bit is

 

changed from a 0 to a 1.

Autonegotiation

Interrupt generated when the autonegotiation complete

complete

(AUTOCMPLT) bit is changed from a 0 to a 1.

Other event

Other events that may require the management information

 

base (MIB) statistics updated if a counter has reached its half-

 

way point. These counters should clear when read. This ac-

 

tion also disables the counter event function.

 

 

The design of the interrupt-generating logic in the PHY should minimize the number of interrupts generated so that overall system performance is not im- pacted. To achieve this, the events that cause an interrupt are detected by change and not by absolute value. The host, when interrupted, reads the PHY generic status register, followed by the PHY specific status register. This clears the interrupt, as well as clearing the bits that needs to be counted in the MIB.

There is only one deviation from this behavior associated with the LINK bit. This bit needs to inform the host of a change in link status if the last read value was different than the current value. With the exception of LINK=FALSE dur- ing a LINK=TRUE condition, this condition is latched by the PHY and held until the host reads the link fail condition. Since the TxJabber, RemoteFault, and XtalOk conditions are either counted or start a host recovery process, they need only cause an event when they are first set. The JABBER bit should be cleared on the read that reads this bit as a 1, otherwise the next interrupt will count this set bit, corrupting the MIB statistics.

The 802.3u standard provides for communication with the PMI via the two management interface MII pins: MDIO and MDCLK. The MDCLK signal is

Physical Interface (PHY)

7-5

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Texas Instruments TNETE211, TNETE110A, TNETE100A ±2. Possible Sources of MII Event Interrupts, Name Function, Link, Between

TNETE110A, TNETE211, TNETE100A specifications

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