Texas Instruments TNETE211, TNETE110A, TNETE100A manual PCI Configuration Space, PCI Nvram

PCI Configuration Space

2.2 PCI Configuration Space

Figure 2±2. The PCI Configuration Space Registers

	Byte 3		Byte 2	Byte 1		Byte 0
31						0
		Device ID			Vendor ID
		Status			Command
	Base class		Subclass	Program interface		Revision
	(02h)			(00h)
	Reserved		Reserved	Latency		Cache line
	(00h)		(00h)	timer		size
			I/O base address
			Memory base address
			Reserved (00h)
			Cardbus CIS Pointer
			Reserved (00h)
			BIOS ROM base address
			Reserved (00h)
			Reserved (00h)
	Max_Lat		Min_Gnt	Int pin(01h)		Interrupt line
			Reserved (00h)			Reset control
			Reserved (00h)
			Reserved (00h)			IntDis
			Reserved (00h)
			Reserved (00h)			PCI NVRAM

Reserved (00h)

00h read only

04h read/write

08h read only

0Ch read/write

10h read/write

14h read/write

18h

28h

2Ch

30h read/write

34h

38h

3Ch read/write 40h read/write 44h

48h

read only

B4h

read only

FFh

Register configuration space information fields are needed to identify a board in a slot to a driver. The functional purpose of the board, the manufacturer, the revision, and several bus requirements can be obtained by inspecting these parameters. The PCI configuration space uses these registers which are called out in the PCI Local Bus Specification. These enable the PCI system to:

- Identify the ThunderLAN controller. This includes setting the interrupt as- signed to ThunderLAN.

-Map the host registers using either the I/O base address register or the memory base address register. The driver uses the address contained in these registers to access ThunderLAN's internal registers.

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