External Devices

2.6 External Devices

This following section discusses the manner in which the ThunderLAN control- ler interfaces to external devices. These devices include:

-A BIOS ROM

-Light emitting diodes (LEDs)

-A serial EEPROM

-Any devices (PMIs/PMDs) attached to the MDIO/MDCLK serial interface of the MII

2.6.1BIOS ROM

A BIOS ROM is supported with two external latches and a memory device. A memory-space base register is implemented at location 0x30h in the PCI con- figuration space, with 16 bits forced to fixed values. This reserves 64K bytes of memory space. A PCI memory read is requested, and if the upper 16 bits match the value posted in the BIOS ROM base address, hardware state ma- chines begin a special cycle that posts the two eight-bit parts of the address along with address strobes on the EAD[7::0] pins. The EAD[7::0] lines act as an output bus during the output of the low eight bits signaled by the EALE strobe, and the output of the next eight bits signaled by the EXLE strobe. They act as an input bus when accepting the data from the EPROM which is sig- naled by the EOE EPROM output enable strobe. This interface is designed to support all types of read cycles from the host: byte, word, and long word. Four cycles are automatically done to prepare a 32-bit response to the PCI read cycle. During the state machine's execution, the PCI read cycle sends wait states to the host processor. Writes to the EPROM memory space are ac- cepted and performed, but are internally ignored.

2.6.2LEDs

The EAD[7::0] bus is an output bus when not involved in EPROM read cycles. These pins are driven with the inverse of the pattern written into LEDreg, an internal register. To access this register, a 0x44 is written to the DIO_ADR host register, then either a byte write to the DIO_DATA host register or a read/ modify/write to the whole DIO_DATA host register is done to deposit the value into LEDreg. A logic 1 in the register translates to an active low on the external output pin. All bits in this register are set to 0 on the Ad_Rst bit, or when the external reset, PRST#, is activated.

The meaning assigned to the LEDs, which LEDs are actually implemented, and the times to set and clear them are all programmable. Texas Instruments

ThunderLAN Registers

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Texas Instruments TNETE211, TNETE110A, TNETE100A manual External Devices, Bios ROM, LEDs
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TNETE110A, TNETE211, TNETE100A specifications

Texas Instruments has been a leader in developing innovative semiconductor solutions, and their Ethernet PHY (Physical Layer Transceiver) family, specifically the TNETE100A, TNETE211, and TNETE110A, exemplifies this commitment to excellence. These devices are designed to address the needs of a variety of applications, ranging from industrial automation to consumer electronics.

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