PCI Command Register @ 04h, Ser | Texas Instruments TNETE110A

PCI Configuration Registers

Should autoconfiguration fail (bad checksum), this register is loaded with the ThunderLAN device ID of 0500h.

A.1.4 PCI Command Register (@ 04h)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			Reserved				SER	Res	Par		Reserved		BM	Mem	I/O
			Reserved				En	Res	En		Reserved		En	En	En
							En		En				En	En	En

Table A±1. PCI Command Register Bits

Bit	Name	Function
15±9	Reserved	Writes to these bits are ignored; bits are always read as 0.
8	SER_En	PSERR# driver enable: A value of 1 enables the adapter PSERR# driver. A value of
		0 disables the driver.
7	Reserved	Writes to this bit are ignored; bit is always read as 0.
6	PAR_En	Parity enable: Enables the adapter PCI parity checking. A value of 1 allows the adapter
		to check PCI parity, a value of 0 causes PCI parity errors to be ignored.
5±3	Reserved	Writes to these bits are ignored; bits are always read as 0.
2	BM_En	Bus master enable: Enables the adapter as a PCI bus master. A value of 1 enables bus
		master operations, a value of 0 disables them.
1	Mem_En	Memory enable: Enables memory-mapped accesses to the adapter. A value of 0 dis-
		ables response to memory-mapped accesses. A value of 1 enables response to
		memory-mapped accesses.
0	I/O_En	I/O Enable: Enables I/O mapped accesses to the adapter. A value of 0 disables re-
		sponse to I/O accesses. A value of 1 enables response to I/O accesses.

A-5

TNETE110A, TNETE211, TNETE100A specifications

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Texas Instruments TNETE110A PCI Command Register @ 04h, Table A±1. PCI Command Register Bits, Ser

Models: TNETE110A TNETE211 TNETE100A

A.1.4 PCI Command Register (@ 04h)

SER

Table A±1. PCI Command Register Bits

Bit

TNETE110A, TNETE211, TNETE100A specifications