Host Registers, Offset, +12, Diodata | Texas Instruments TNETE100A

Host Registers

2.3 Host Registers

Figure 2±4. Host Registers

		Base address
31	16 15	0	offset

	HOST_CMD		+0
			+4
	CH_PARM		+4
			+8
	HOST_INT	DIO_ADR	+8
			+12
	DIO_DATA		+12

ThunderLAN implements the host registers shown above. These are the pri- mary control points for ThunderLAN. Through the host registers, a driver can:

-Reset the ThunderLAN controller

-Start transmit and receive channels

-Handle interrupts: Acknowledge interrupts, turn certain kinds of interrupts on or off, or pace interrupts with the host

-Access the internal registers

-Access the internal SRAM for diagnostic purposes

The HOST_CMD register gives commands to the ThunderLAN controller. It is used in conjunction with the CH_PARM register to start the transmit and re- ceive processes (Tx GO/Rx GO). It is also used in conjunction with the HOST_INT register to acknowledge (ack) interrupts. Through HOST_CMD, interrupt pacing can be selected.

The CH_PARM register is used to give the physical addresses of a transmit or receive list to ThunderLAN's direct memory access (DMA) controller. Thun- derLAN uses the address in the CH_PARM register to DMA data into or out of its FIFOs. In an adapter check, an error condition where ThunderLAN must be reset, CH_PARM contains information on the nature of the error.

The HOST_INT register contains information on the type of interrupt that was given to the host processor. It is also used with the CH_PARM register to indi- cate adapter checks. HOST_INT is designed to make interrupt handling rou- tines simple and powerful. The last two significant bits are set to 0 so that this register may be used as a table offset in a jump table. The bit definitions are mapped to the most significant word (MSW) of the HOST_CMD register. This allows acknowledging of interrupt operations by simply taking the value in HOST_INT and writing it to HOST_CMD.

The DIO_ADR and DIO_DATA registers work in tandem to allow accesses to the internal DIO registers and SRAM. The value in DIO_ADR selects the regis- ter or memory locations to be accessed.

ThunderLAN Registers

2-9

TNETE110A, TNETE211, TNETE100A specifications

Texas Instruments has been a leader in developing innovative semiconductor solutions, and their Ethernet PHY (Physical Layer Transceiver) family, specifically the TNETE100A, TNETE211, and TNETE110A, exemplifies this commitment to excellence. These devices are designed to address the needs of a variety of applications, ranging from industrial automation to consumer electronics.

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Texas Instruments TNETE100A Host Registers, Offset, Hostcmd Chparm Hostint Dioadr, +12, Diodata

Models: TNETE110A TNETE211 TNETE100A

2.3 Host Registers

Figure 2±4. Host Registers

offset

HOST_CMD

CH_PARM

HOST_INT

DIO_ADR

+12

DIO_DATA

ThunderLAN Registers

TNETE110A, TNETE211, TNETE100A specifications