Texas Instruments TNETE110A, TNETE211, TNETE100A manual Register Addresses

Register Addresses

2.1 Register Addresses

The following figure shows the various register spaces provided by Thunder- LAN. It also shows how a driver uses ThunderLAN's registers to interface to external devices such as PHYs, BIOS ROMs, and EEPROMs.

Figure 2±1. How ThunderLAN Registers are Addressed

PCI

ThunderLAN

Host registers

HOST CMD SRAM

CH PARM

HOST INT	Internal/DIO registers		MII/PHY registers
DIO ADR	NetCmd		Generic
DIO DATA	NetSts	MDIO/MDCLK	Autonegotiation
PCI registers	NetSio		Reserved
I/O base	AREG0±3		PHY specific
address	HASH
Memory
	Statistics
base address		EDIO/EDCLK
	registers
BIOS ROM			Serial EEPROM
	LEDreg
base address
PCI NVRAM			BIOS ROM
			LED

LED IF

One block of registers, the host registers, appear at a programmable place in memory or port address space, directly on the PCI bus. The beginning address is determined by the value written into the PCI configuration space base ad- dress registers. Once the base register's address is determined, ThunderLAN reads and writes to these registers like ordinary memory or I/O ports. Since the ThunderLAN devices are directly connected to the PCI, there is no external decode logic that generates a chip selectÐall the decode is done internally.

ThunderLAN's internal/DIO registers are accessed via the DIO_ADR and DIO_DATA registers in the host register group. An address is placed in the host DIO_ADR register, and the data to be read or written to the DIO register is read or written to the DIO_DATA register. The internal/DIO register space is refer- enced indirectly via the host registers to minimize the amount of host address space required to support the ThunderLAN controller. External devices and their data are also reached via indirect reference through the host registers

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