PHY Initialization
7-9
Physical Interface (PHY)
7.4 PHY Initialization
The driver initializes each MII-attached PHY. Since there may be more than
one PHY attached to the MII, proper initialization ensures that one and only
one PHY is active and driving the MII. (The condition where more than one
PHY drives the MII at the same time is termed contention.)
Each MII-equipped PHY device has a control register at offset 0x00h. In
ThunderLAN, this register is called GEN_ctl. The effect of asserting the isolate
bit in this register is that the PHY does not drive any wire, port, or magnetics
it is connected to, and it Hi-Zs the interface to the MII data bus. The PHY still
pays attention and responds to requests from the MII management interface,
consisting of the MDIO/MDCLK lines.
Nominal treatment of the attached PHY requires 32 clock cycles be applied to
the PHY to synchronize the serial management interfaces. This is required on
each access, unless it responds to a fast start delimiter. If a PHY has this fea-
ture, synchronization is only required on the first access. The clock cycles are
generated through the NetSio register.