PCI Configuration Registers

A.1.18 PCI Min_Gnt (@ 3Eh) and Max_Lat (@ 3Fh) Registers

These byte registers are used to specify the adapter's desired settings for la- tency timers. For both registers, the value specifies a period of time in units of 250 ns (quarter microsecond).

These registers are loaded from an external serial EEPROM on the falling edge of PCI reset, during autoconfiguration. Should autoconfiguration fail (bad checksum), then these registers are loaded with the default values, which are currently 0x00h.

The Min_Gnt register is used for specifying how long a burst period the device needs (assuming a 33-MHz clock). The Max_Lat register is used for specifying how often the device needs to gain access to the PCI bus.

A.1.19 PCI Reset Control Register (@ 40h)

This register is used to disable automatic software resets. The automatic soft- ware reset feature is for machines that do not assert the PCI bus PRST# line during soft (Ctrl-Alt-Del) resets, but still performs diagnostics on PCI bus de- vices. The automatic software reset feature ensures the adapter is reset (and therefore not performing PCI bus master operations) before diagnostics are started.

Soft resets are detected as the deassertion of the BM_En, Mem_En, and IO_En bits in the PCI command register. This differentiates soft resets from bus master disables, which may take place in some systems.

When a soft reset is disabled and the host machine is rebooted, ThunderLAN must be reconfigured without resetting the adapter.

 

 

 

Byte 0

 

 

 

 

7

6

5

4

3

2

1

0

 

 

 

Reserved (0)

 

 

 

SRDIS

 

 

 

 

 

 

 

 

Table A±4. PCI Reset Control Register Bits

Bit

Name

Function

7±1

Reserved

These bits are always read as 0. Writes to these bits are ignored.

0

SRDIS

Soft reset disable: This bit is used to disable automatic software adapter resets. When

 

 

this bit is set to a 1, an adapter software reset (equivalent to writing a 1 to the Ad_Rst

 

 

bit) takes place whenever the BM_En, Mem_En, and IO_En bits in the PCI command

 

 

register are 0. When SRDIS is set to a 1, 0s in these bits do not cause a software reset.

 

 

 

A-10

Page 122 Page 124
Page 123
Image 123
Texas Instruments TNETE211, TNETE110A PCI MinGnt @ 3Eh and MaxLat @ 3Fh Registers, PCI Reset Control Register @ 40h, Srdis
Page 122 Page 124

TNETE110A, TNETE211, TNETE100A specifications

Texas Instruments has been a leader in developing innovative semiconductor solutions, and their Ethernet PHY (Physical Layer Transceiver) family, specifically the TNETE100A, TNETE211, and TNETE110A, exemplifies this commitment to excellence. These devices are designed to address the needs of a variety of applications, ranging from industrial automation to consumer electronics.

The TNETE100A is a highly versatile Ethernet PHY capable of supporting 10/100 Mbps Ethernet connectivity. One of its main features is the low power consumption, which makes it an ideal choice for battery-operated devices. It incorporates advanced power management technologies, ensuring that the device operates efficiently while maintaining high performance. The TNETE100A also supports Auto-Negotiation, allowing for seamless communication between devices at different speeds, thereby enhancing flexibility in network configurations.

Moving to the TNETE211, this device supports 10/100/1000 Mbps Ethernet, making it suitable for high-speed networking applications. This PHY integrates features such as Energy Efficient Ethernet (EEE), which reduces power consumption during low-traffic periods, aligning with the contemporary demand for energy efficiency in networking equipment. The TNETE211 is engineered with robust EMI (Electromagnetic Interference) performance and provides multiple interface options, making it a versatile choice for embedded systems and networking applications.

The TNETE110A stands out in the lineup as a sophisticated device that supports both Fast Ethernet and Gigabit Ethernet. This PHY utilizes advanced signal processing techniques to ensure superior link robustness and performance in noisy environments. Its features include an integrated transformer driver, which simplifies PCB design and allows for compact device layouts. Additionally, the TNETE110A is designed to be fully compliant with Ethernet standards, ensuring reliable interoperability with other network components.

All three PHYs leverage Texas Instruments' expertise in integrated circuit design, resulting in low jitter and high signal integrity, essential for modern communication standards. They are optimized for a wide range of temperatures, making them suitable for harsh industrial applications. With built-in diagnostic capabilities, these devices also enable efficient fault detection and troubleshooting in network infrastructures.

In summary, the Texas Instruments TNETE100A, TNETE211, and TNETE110A are exemplary Ethernet PHY devices, each tailored to meet specific networking needs while adhering to stringent efficiency and performance criteria. Their advanced features, technologies, and reliability make them pivotal components in today's fast-paced digital landscape.
Top Page Image Contents