base + 0816

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

base + 0A16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt Control Register

The interrupt level and the interrupt source are controlled by the interrupt control register. There are several sources of interrupt. A logical OR is performed on the enabled sources to determine if an IRQ should be pulled. This allows a user to set an interrupt if any channel exceeds a predetermined level or if data is available.

Bits 0, 1 and 2 control the interrupt level (1 - 7). Level 0 (000) is not a valid setting. The enable bit (bit 3) allows an IRQ to occur when it is set high. All interrupt sources are edge sensitive. If a masked latched interrupt source is high during the interrupt acknowledge (IACK) cycle, the latch of the source is cleared and will not be set until another edge from the source occurs. :

base + 0C16

15

14

13

12

11

10

9

 

8

7

6

5

4

3

 

2

1

 

0

Write*

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Enable

 

L2

L1

 

L0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read**

 

TRIG

DONE

PRE

OVER

CH4

CH3

CH2

 

CH1

 

undefined

Enable

 

Interrupt Level

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*WRITE BITS (Interrupt Control Register)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bits 0-2

 

L0-2

Specifies the interrupt level (1 - 7); “001” = 1, “111” = 7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 3

 

Enable

Enable the interrupt; “1” = interrupt enabled, “0” = interrupt disabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

**READ BITS (Interrupt Control Register)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 15

 

TRIG

A trigger has been received after pre-trigger acquisition is done.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 14

 

DONE

Memory is full or post trigger acquisition is done.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 13

 

PRE

Pre-trigger data has been acquired.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 12

 

OVER

A dangerous OVERvoltage caused the channel input relay to open.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 11

 

CH4

Channel 4 exceeded the set limit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 10

 

CH3

Channel 3 exceeded the set limit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 9

 

CH2

Channel 2 exceeded the set limit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 8

 

CH1

Channel 1 exceeded the set limit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Appendix B

 

 

 

 

 

 

 

 

 

 

 

Register-Based Programming

129

Page 129
Image 129
Agilent Technologies E1563A, E1564A user manual Interrupt Control Register, Appendix B Register-Based Programming 129

E1563A, E1564A specifications

Agilent Technologies, a prominent player in the field of electronic measurement, offers a range of products designed for various testing applications. Among their notable offerings are the E1564A and E1563A modules. Both models are designed for high-performance testing and measurement, catering particularly to the needs of engineers and technicians in the telecommunications and wireless industries.

The Agilent E1564A is a high-speed data and synchronization generation module, specifically tailored for advanced signal analysis. One of its primary features is its ability to provide a wide range of modulation types, including QPSK and 16QAM, which are essential for testing modern communication systems. The module also boasts a flexible output that supports multiple channels, making it efficient for testing complex systems where multiple data streams are present. Its exceptional performance in generating accurate waveforms enables engineers to perform thorough tests and validations on their devices.

On the other hand, the E1563A module is predominantly focused on protocol analysis and provides engineers with insights into the behavior of their communication systems. This module features comprehensive support for various communication protocols, making it invaluable when debugging and validating designs. Engineers can utilize the extensive measurement capabilities of the E1563A to analyze data integrity and system performance, ensuring that their products meet required specifications.

Both modules leverage advanced technologies from Agilent, ensuring high accuracy and reliability in measurements. They are equipped with powerful processing capabilities that allow for real-time data analysis, a critical aspect when working with high-frequency signals. Furthermore, these modules are designed for seamless integration into Agilent’s test and measurement platforms, enhancing usability and facilitating complex testing scenarios.

In summary, the Agilent E1564A and E1563A modules represent cutting-edge solutions for engineers involved in testing and validating communication systems. With their robust features, including support for various modulation schemes and protocol analysis, these modules enable efficient and accurate measurements. The commitment to quality and precision from Agilent Technologies continues to make these devices essential tools in the industry, helping engineers push the boundaries of innovation in telecommunications.