Index 173

S (continued)

STATus subsystem (cont’d)
STATus:QUEStionable:CONDition?,96
STATus:QUEStionable:ENABle,96
STATus:QUEStionable:ENABle?,96
STATus:QUEStionable[:EVENt]?,96
SYSTem subsystem
SYSTem:ERRor?,97
SYSTem:VERSion?,97

T

Test Accuracy Ratio (TAR),158
test equipment, recommended,151
TEST subsystem
TEST:ERRor?,98
TEST:NUMBer?,98
TEST:TST[:RESults]?,103
Trigger/Interrupt Level Channel 1 register,134
Trigger/Interrupt Level Channel 2 register,135
Trigger/Interrupt Level Channel 3 register,135
Trigger/Interrupt Level Channel 4 register,136
Trigger Control register,137
trigger sources,37
TRIGger subsystem
TRIGger[:IMMediate],104
TRIGger:LEVel,104
TRIGger:LEVel?,105
TRIGger:MODE,105
TRIGger:MODE?,106
TRIGger:SLOPe[<n>],106
TRIGger:SLOPe[<n>]?,107
TRIGger:SOURce[<n>],107
TRIGger:SOURce[<n>]?,108
triggering the digitizers,37

V

verification tests,151

W

WARNINGS,10
Warnings,17
warranty statement,9
WRITE registers,124

Z

Zero Adjustment procedure,165
Zero Offset verification test,154